UPD70F3714GC-8BS-A Renesas Electronics America, UPD70F3714GC-8BS-A Datasheet - Page 181

• Manufacturer Part Number: UPD70F3714GC-8BS-A
• Description: MCU 32BIT V850ES/LX2 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Ix2r

Specifications of UPD70F3714GC-8BS-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, UART/USART
• Peripherals: LVD, PWM, WDT
• Number Of I /o: 39
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

counts each time the valid edge of external event count input is detected. Additionally, the set value of the TPkCCR0
register is transferred to the CCR0 buffer register.
cleared to 0000H, and a compare match interrupt request signal (INTTPkCC0) is generated.
been detected “value set to TPkCCR0 register” times. After that, the INTTPkCC0 signal is generated each time the
valid edge of the external event count has been detected “value set to TPkCCR0 register + 1” times.
When the TPkCE bit is set to 1, the value of the 16-bit counter is cleared from FFFFH to 0000H. The counter
When the count value of the 16-bit counter matches the value of the CCR0 buffer register, the 16-bit counter is
The INTTPkCC0 signal is generated for the first time when the valid edge of the external event count input has
TPkCTL0
TPkCTL1
TPkIOC2
(a) TMPk control register 0 (TPkCTL0)
(b) TMPk control register 1 (TPkCTL1)
(c) TMPk I/O control register 2 (TPkIOC2)
(d) TMPk counter read buffer register (TPkCNT)
(e) TMPk capture/compare register 0 (TPkCCR0)
The count value of the 16-bit counter can be read by reading the TPkCNT register.
If the TPkCCR0 register is set to D
reached (D
second compare match interrupt request signal (INTTPkCC0) is generated when the number of
external event counts has reached (D
TPkCE
Figure 6-18. Register Setting for Operation in External Event Count Mode (1/2)
0/1
0
0
0
) and the first compare match interrupt request signal (INTTPkCC0) is generated. The
TPkEST
0
0
0
CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP)
TPkEEE
0
0
0
User’s Manual U17716EJ2V0UD
0
0
0
0
, the count is cleared when the number of external event counts has
0
+ 1).
TPkEES1
0/1
0
0
TPkEES0 TPkETS1 TPkETS0
TPkCKS2 TPkCKS1 TPkCKS0
TPkMD2 TPkMD1 TPkMD0
0/1
0
0
0
0
0
0
0
1
Select valid edge
of external event
count input (TIPk0 pin)
0: Stop counting
1: Enable counting
0, 0, 1:
External event count mode
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