UPD70F3714GC-8BS-A Renesas Electronics America, UPD70F3714GC-8BS-A Datasheet - Page 213

• Manufacturer Part Number: UPD70F3714GC-8BS-A
• Description: MCU 32BIT V850ES/LX2 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Ix2r

Specifications of UPD70F3714GC-8BS-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, UART/USART
• Peripherals: LVD, PWM, WDT
• Number Of I /o: 39
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

<1> Count operation start flow
<2> TPmCCR0, TPmCCR1 register
(TPmCKS0 to TPmCKS2 bits)
setting change flow (cycle only)
Setting of TPmCCR0 register
Setting of TPmCCR1 register
Register initial setting
TPmCCR0 register,
TPmCTL1 register,
TPmIOC0 register,
TPmCCR1 register
TPkIOC2 register,
TPmCTL0 register
Remark
TPmCE bit = 1
START
m = 0, 2, 3
k = 0, 2
a = 0, 1
Figure 6-34. Software Processing Flow in PWM Output Mode (2/2)
CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP)
Initial setting of these
registers is performed
before setting the
TPnCE bit to 1.
The TPmCKS0 to
TPmCKS2 bits can be
set at the same time
when counting is
enabled (TPmCE bit = 1).
Writing same value
(same as preset value of
the TPmCCR1 register)
to the TPmCCR1 register
is necessary only when
the set cycle is changed.
When the counter is
cleared after setting,
the value of the TPmCCRa
register is transferred to the
CCRa buffer register.
User’s Manual U17716EJ2V0UD
<3> TPmCCR0, TPmCCR1 register
<4> TPmCCR0, TPmCCR1 register
<5> Count operation stop flow
setting change flow (duty only)
setting change flow (cycle and duty)
Setting of TPmCCR1 register
Setting of TPmCCR0 register
Setting of TPmCCR1 register
TPmCE bit = 0
STOP
Counting is stopped.
Only writing of the TPmCCR1
register must be performed
when the set duty factor is
changed. When the counter is
cleared after setting, the
value of compare register a
is transferred to the CCRa
buffer register.
When the counter is
cleared after setting,
the value of compare
register a is transferred
to the CCRa buffer register.
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