UPD70F3714GC-8BS-A Renesas Electronics America, UPD70F3714GC-8BS-A Datasheet - Page 368

• Manufacturer Part Number: UPD70F3714GC-8BS-A
• Description: MCU 32BIT V850ES/LX2 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Ix2r

Specifications of UPD70F3714GC-8BS-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, UART/USART
• Peripherals: LVD, PWM, WDT
• Number Of I /o: 39
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

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366
(3) TMQ1 option register 2 (TQ1OPT2)
The TQ1OPT2 register is an 8-bit register that controls the timer Q1 option function.
This register can be rewritten when the TQ1CTL0.TQ1CE bit is 1. However, rewriting the TQ1DTM bit is
prohibited when the TQ1CE bit is 1. The same value can be rewritten.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
TQ1OPT2
After reset: 00H
Remark
Cautions 1. When
TQ1RDE
TQ1DTM
TQ1RDE
Rewriting the TQ1DTM bit is disabled during timer operation. If it is rewritten by
mistake, stop the timer operation by clearing the TQ1CE bit to 0, and re-set the
TQ1DTM bit.
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0
1
0
1
TQ1DTM TQ1ATM03 TQ1ATM02 TQ1AT03 TQ1AT02 TQ1AT01 TQ1AT00
m = 1 to 3
Do not cull transfer (transfer timing is generated every time at crest
and valley).
Cull transfer at the same interval as interrupt culling set by the TQ1OPT1
register.
Dead-time counter counts up normally and, if TOQ1m output of TMQ1 is
at a narrow interval (TOQ1m output width < dead-time width), the
dead-time counter is cleared and counts up again.
Dead-time counter counts up normally and, if TOQ1m output of TMQ1 is
at a narrow interval (TOQ1m output width < dead-time width), the
dead-time counter counts down and the dead-time control width is
automatically narrowed.
CHAPTER 9 MOTOR CONTROL FUNCTION
2. To generate the dead-time period, set the TQ1DTC register to 1 or
R/W
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TQ1OPT1.TQ1ID0 bits are set to other than 00000), be sure to set the
TQ1RDE bit to 1.
Therefore, the interrupt and transfer are generated at the same timing.
The interrupt and transfer cannot be set separately. If the interrupt
and transfer are set separately (TQ1RDE bit = 0), transfer is not
performed normally.
more.
When the operation is stopped (TQ1CTL0.TQ1CE bit = 0), the dead-
time period is not generated and the output level of the TOQ1T1 to
TOQ1T3 pins and TOQ1B1 to TOQ1B3 pins will be in the initial status.
For the system protection, therefore, before operation is being
stopped, set the TOQ1T1 to TOQ1T3 and TOQ1B1 to TOQ1B3 pins to
the high impedance state, or set the output level of pins and switch
them to the port mode.
If a dead time period is not needed, set the TQ1DTC register to 0.
User’s Manual U17716EJ2V0UD
Address: FFFFF621H
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Dead-time counter operation mode selection
using
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Transfer culling enable
interrupt
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culling
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(the
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TQ1OPT1.TQ1ID4
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(1/2)
to