UPD70F3714GC-8BS-A Renesas Electronics America, UPD70F3714GC-8BS-A Datasheet - Page 256

• Manufacturer Part Number: UPD70F3714GC-8BS-A
• Description: MCU 32BIT V850ES/LX2 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Ix2r

Specifications of UPD70F3714GC-8BS-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, UART/USART
• Peripherals: LVD, PWM, WDT
• Number Of I /o: 39
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

254
Table 7-5. Function of Capture/Compare Register in Each Mode and How to Write Compare Register
Interval timer
External event counter
External trigger pulse output
One-shot pulse output
PWM output
Free-running timer
Pulse width measurement
(a) Function as compare register
(b) Function as capture register (TQ0CCR1 register only)
The following table shows the functions of the capture/compare register in each mode, and how to write data to
the compare register.
Notes 1. TMQ0 only
Remark
The TQnCCR1 register can be rewritten even when the TQnCTL0.TQnCE bit = 1.
The set value of the TQnCCR1 register is transferred to the CCR1 buffer register. When the value of the
16-bit counter matches the value of the CCR1 buffer register, a compare match interrupt request signal
(INTTQnCC1) is generated. If TOQ01/TOQH01 pin output is enabled at this time, the output of the
TOQ01/TOQH01 pin is inverted (the TOQ11 and TOQH11 pins are not provided).
The compare register is not cleared by the TQnCTL0.TQnCE bit = 0.
When the TQ0CCR1 register is used as a capture register in the free-running timer mode, the count value
of the 16-bit counter is stored in the TQ0CCR1 register if the valid edge of the capture trigger input pin
(TIQ01 pin) is detected. In the pulse width measurement mode, the count value of the 16-bit counter is
stored in the TQ0CCR1 register and the 16-bit counter is cleared (0000H) if the valid edge of the capture
trigger input pin (TIQ01 pin) is detected.
Even if the capture operation and reading the TQ0CCR1 register conflict, the correct value of the
TQ0CCR1 register can be read.
The capture register is cleared by the TQ0CTL0.TQ0CE bit = 0.
2. This mode can be set only with the software trigger. No external trigger input pin is available.
3. Writing to the TQ0CCR1 register is the trigger.
Operation Mode
Note 1
For anytime write and batch write, see 7.6 (2) Anytime write and batch write.
Notes 1, 2
Note 1
Note 1
Notes 1, 2
CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ)
Compare register
Compare register
Compare register
Compare register
Compare register
Capture/compare register
Capture register
User’s Manual U17716EJ2V0UD
Capture/Compare Register
Anytime write
Anytime write
Batch write
Anytime write
Batch write
Anytime write
None
How to Write Compare Register
Note 3
Note 3