UPD70F3714GC-8BS-A Renesas Electronics America, UPD70F3714GC-8BS-A Datasheet - Page 299

• Manufacturer Part Number: UPD70F3714GC-8BS-A
• Description: MCU 32BIT V850ES/LX2 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Ix2r

Specifications of UPD70F3714GC-8BS-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, UART/USART
• Peripherals: LVD, PWM, WDT
• Number Of I /o: 39
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

<1> Count operation start flow
<2> TQ0CCR0 to TQ0CCR3 register
<3> TQ0CCR0 register setting change flow
(TQ0CKS0 to TQ0CKS2 bits)
Setting of TQ0CCR0, TQ0CCR2,
Setting of TQ0CCR1 register
Setting of TQ0CCR0 register
Setting of TQ0CCR1 register
TQ0CCR0 to TQ0CCR3
Register initial setting
setting change flow
and TQ0CCR3 registers
TQ0CTL1 register,
TQ0IOC0 register,
TQ0IOC2 register,
TQ0CTL0 register
TQ0CE bit = 1
registers
Remark
START
Figure 7-25. Software Processing Flow in External Trigger Pulse Output Mode (2/2)
a = 0 to 3
Initial setting of these
registers is performed
before setting the
TQ0CE bit to 1.
The TQ0CKS0 to
TQ0CKS2 bits can be
set at the same time
when counting is
enabled (TQ0CE bit = 1).
Trigger wait status
Writing of the TQ0CCR1
register must be performed
after writing the TQ0CCR0,
TQ0CCR2, and TQ0CCR3
registers.
When the counter is cleared
after setting, the value
of the TQ0CCRa register is
transferred to the CCRa buffer
registers.
Writing same value (same as
preset value of the TQ0CCR1
register) to the TQ0CCR1
register is necessary only
when the set cycle is changed.
When the counter is
cleared after setting,
the value of the TQ0CCRa
register is transferred to
the CCRa buffer register.
CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ)
User’s Manual U17716EJ2V0UD
<4> TQ0CCR1 to TQ0CCR3 register
<6> TQ0CCR1 register setting change flow
<7> Count operation stop flow
<5> TQ0CCR2, TQ0CCR3 register
Setting of TQ0CCR1 register
Setting of TQ0CCR1 register
Setting of TQ0CCR1 register
Setting of TQ0CCR2,
Setting of TQ0CCR2,
setting change flow
setting change flow
TQ0CCR3 registers
TQ0CCR3 registers
TQ0CE bit = 0
STOP
Writing of the TQ0CCR1
register must be performed
when the set duty factor is only
changed after writing the
TQ0CCR2 and TQ0CCR3
registers.
When the counter is cleared
after setting, the value of the
TQ0CCRa register is transferred
to the CCRa buffer register.
Writing same value (same as
preset value of the TQ0CCR1
register) to the TQ0CCR1 register
is necessary only when the set
duty factor of TOQ02 and TOQ03
pin outputs is changed.
When the counter is
cleared after setting,
the value of the TQ0CCRa
register is transferred to
the CCRa buffer register.
Only writing of the TQ0CCR1
register must be performed when
the set duty factor is only changed.
When counter is cleared after
setting, the value of the TQ0CCRa
register is transferred to the CCRa
buffer register.
Counting is stopped.
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