UPD70F3714GC-8BS-A Renesas Electronics America, UPD70F3714GC-8BS-A Datasheet - Page 582

• Manufacturer Part Number: UPD70F3714GC-8BS-A
• Description: MCU 32BIT V850ES/LX2 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Ix2r

Specifications of UPD70F3714GC-8BS-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, UART/USART
• Peripherals: LVD, PWM, WDT
• Number Of I /o: 39
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

580
Setting of HALT mode
Notes 1. Non-maskable interrupt request signal (INTWDT) or unmasked maskable interrupt request signal
2. RESET pin input, reset signal generation by watchdog timer overflow (WDTRES), reset signal
3. Unmasked external interrupt request signal (INTP0 to INTP5), unmasked internal interrupt request
4. Unmasked external interrupt request signal (INTP0 to INTP5), unmasked internal interrupt request
5. Oscillation stabilization time count by oscillation stabilization time wait control (OST)
6. Oscillation stabilization time count by oscillation stabilization time wait control (OST)
7. RESET pin input, reset signal generation by low-voltage detection (LVIRES), or reset signal
Interrupt request
generation by low-voltage detection (LVIRES), or reset signal generation by power-on clear
(POCRES).
signal (INTLVI), or unmasked internal interrupt request signal from peripheral functions operable in
IDLE mode (interrupt request signal related to CSIB in slave mode)
signal (INTLVI), or unmasked internal interrupt request signal from peripheral functions operable in
STOP mode (interrupt request signal related to CSIB in slave mode)
The oscillation stabilization time is necessary after release of reset because the PLL is initialized by a
reset. The stabilization time is the time determined by default.
The stabilization time is determined by the setting of the OSTS register.
generation by power-on clear (POCRES).
HALT mode
Wait for stabilization of
(oscillation) and PLL
System reset
Note 1
Note 5
Setting of STOP mode
Note 2
CHAPTER 15 STANDBY FUNCTION
Figure 15-1. Status Transition
User’s Manual U17716EJ2V0UD
Interrupt request
Normal operation mode
Wait for stabilization of
oscillation and PLL
Note 6
STOP mode
System reset
Note 4
Note 5
Note 7
Setting of IDLE mode
Interrupt request
IDLE mode
Wait for stabilization of
(oscillation) and PLL
System reset
Note 3
Note 5
Note 7