UPD70F3714GC-8BS-A Renesas Electronics America, UPD70F3714GC-8BS-A Datasheet - Page 376

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UPD70F3714GC-8BS-A

Manufacturer Part Number
UPD70F3714GC-8BS-A
Description
MCU 32BIT V850ES/LX2 64-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Ix2r
Datasheet

Specifications of UPD70F3714GC-8BS-A

Core Processor
RISC
Core Size
32-Bit
Speed
20MHz
Connectivity
CSI, UART/USART
Peripherals
LVD, PWM, WDT
Number Of I /o
39
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
3.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
UPD70F3714GC-8BS-A
Manufacturer:
Renesas Electronics America
Quantity:
10 000
374
Note HZA0CTL0: TOQH0OFF pin, HZA0CTL1: TOP2OFF pin,
HZAyDCCn
HZAyDCFn
• Pins can function as output pins when the HZAyDCM bit = 0, regardless of the
• If an edge indicating abnormality is input to the external pin
• The HZAyDCCn bit is always 0 when it is read.
• The HZAyDCCn bit is invalid even if it is set to 1 when the HZAyDCEn bit = 0.
• Simultaneously setting the HZAyDCTn and HZAyDCCn bits to 1 is prohibited.
status of the external pin
HZAyDCNn and HZAyDCPn bits) when the HZAyDCM bit = 1, the HZAyDCCn
bit is invalid even if it is set to 1.
0
1
0
1
HZA1CTL0: TOQ1OFF pin, HZA1CTL1: TOP3OFF pin
No operation
Pins that have gone into a high-impedance state are output-enabled by
software and the HZAyDCFn bit is cleared to 0.
Indicates that output of the pin is enabled.
• This bit is cleared to 0 when the HZAyDCEn bit = 0.
• This bit is cleared to 0 when the HZAyDCCn bit = 1.
Indicates that the pin goes into a high-impedance state.
• This bit is set to 1 when the HZAyDCTn bit = 1.
• This bit is set to 1 when an edge indicating abnormality is input to the
external pin
HZAyDCNn and HZAyDCPn bits).
CHAPTER 9 MOTOR CONTROL FUNCTION
Note
Note
User’s Manual U17716EJ2V0UD
High-impedance output control clear bit
(which is detected according to the setting of the
.
High-impedance output status flag
Note
(which is set by the
(2/2)

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