UPD70F3714GC-8BS-A Renesas Electronics America, UPD70F3714GC-8BS-A Datasheet - Page 34

• Manufacturer Part Number: UPD70F3714GC-8BS-A
• Description: MCU 32BIT V850ES/LX2 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Ix2r

Specifications of UPD70F3714GC-8BS-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, UART/USART
• Peripherals: LVD, PWM, WDT
• Number Of I /o: 39
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Caution Even if bit 0 of EIPC, FEPC, or CTPC is set (1) by the LDSR instruction, bit 0 is ignored during return
3.2.2
the system register load/store instructions (LDSR, STSR instructions).
32
Notes 1. Since only one set of these registers is available, the contents of this register must be saved by the
Register No.
System registers control the status of the CPU and hold interrupt information.
Read from and write to system registers are performed by setting the system register numbers shown below with
21 to 31
System
6 to 15
16
17
18
19
20
0
1
2
3
4
5
2. Can be accessed only after the DBTRAP instruction or illegal opcode is executed and before the DBRET
System register set
with the RETI instruction following interrupt servicing (because bit 0 of PC is fixed to 0). When
setting a value to EIPC, FEPC, and CTPC, set an even number (bit 0 = 0).
program when multiple interrupt servicing is enabled.
instruction is executed.
Interrupt status saving register (EIPC)
Interrupt status saving register (EIPSW)
NMI status saving register (FEPC)
NMI status saving register (FEPSW)
Interrupt source register (ECR)
Program status word (PSW)
Reserved numbers for future function expansion (The operation is not guaranteed
if accessed.)
CALLT execution status saving register (CTPC)
CALLT execution status saving register (CTPSW)
Exception/debug trap status saving register (DBPC)
Exception/debug trap status saving register (DBPSW)
CALLT base pointer (CTBP)
Reserved numbers for future function expansion (The operation is not guaranteed
if accessed.)
Table 3-2. System Register Numbers
System Register Name
CHAPTER 3 CPU FUNCTION
User’s Manual U17716EJ2V0UD
Note 1
Note 1
Operand Specification Enabled
Instruction
Yes
Yes
LDSR
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
Note 2
Note 2
Instruction
Yes
Yes
STSR
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
Note 2
Note 2