UPD70F3714GC-8BS-A Renesas Electronics America, UPD70F3714GC-8BS-A Datasheet - Page 417

• Manufacturer Part Number: UPD70F3714GC-8BS-A
• Description: MCU 32BIT V850ES/LX2 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Ix2r

Specifications of UPD70F3714GC-8BS-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, UART/USART
• Peripherals: LVD, PWM, WDT
• Number Of I /o: 39
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(2) Tuning operation clearing procedure
(3) When not tuning TMP1
(4) Basic operation of TMP1 during tuning operation
To clear the tuning operation and exit the 6-phase PWM output mode, set the TMP1 and TMQ1 registers using
the following procedure.
<1> Clear the TQ1CTL0.TQ1CE bit to 0 and stop the timer operation.
<2> Clear the TP1CTL0.TP1CE bit to 0 so that TMP1 can be separated.
<3> Stop the timer output by using the TQ1IOC0 register.
<4> Clear the TP1CTL1.TP1SYE bit to 0 to clear the tuning operation.
Caution Manipulating (reading/writing) the other TMQ1, TMP1, and TMQ1 option registers is prohibited
When the match interrupt signal of TMP1 is not necessary as the conversion trigger source that starts A/D
converters 0 and 1, TMP1 can be used independently as a separate timer without being tuned. In this case,
the match interrupt signal of TMP1 cannot be used as a trigger source to start A/D conversion in the 6-phase
PWM output mode.
TQ1OPT3.TQ1AT10 to TQ1OPT3.TQ1AT13 bits to 0.
The other control bits can be used in the same manner as when TMP1 is tuned.
If TMP1 is not tuned, the compare registers (TP1CCR0 and TP1CCR1) of TMP1 are not affected by the setting
of the TQ1OPT0.TQ1CMS and TQ1OPT2.TQ1RDE bit. For the initialization procedure when TMP1 is not
tuned, see (b) to (e) in 9.4.5 (1) Tuning operation starting procedure. (a) is not necessary because it is a
step used to set TMP1 for the tuning operation.
The 16-bit counter of TMP1 only counts up. The 16-bit counter is cleared by the set cycle value of the
TQ1CCR0 register and starts counting from 0000H again. The count value of this counter is the same as the
value of the 16-bit counter of TMQ1 when it counts up. However, it is not the same when the 16-bit counter of
TMP1 counts down.
• When TMQ1 counts up (same value)
• When TMQ1 counts down (not same value)
16-bit counter of TMQ1: 0000H → M (counting up)
16-bit counter of TMP1: 0000H → M (counting up)
16-bit counter of TMQ1: M + 1 → 0001H (counting down)
16-bit counter of TMP1: 0000H → M (counting up)
until the TQ1CE bit is set to 0 and then the TP1CE bit is set to 0.
Therefore, fix the TQ1OPT2.TQ1AT00 to TQ1OPT2.TQ1AT03 bits and the
CHAPTER 9 MOTOR CONTROL FUNCTION
User’s Manual U17716EJ2V0UD
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