UPD70F3714GC-8BS-A Renesas Electronics America, UPD70F3714GC-8BS-A Datasheet - Page 427

• Manufacturer Part Number: UPD70F3714GC-8BS-A
• Description: MCU 32BIT V850ES/LX2 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Ix2r

Specifications of UPD70F3714GC-8BS-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, UART/USART
• Peripherals: LVD, PWM, WDT
• Number Of I /o: 39
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

10.4 Operation
the watchdog timer has started operating, a non-maskable interrupt request signal (INTWDT) or a reset signal
(WDTRES) is generated due to watchdog timer overflow, depending on the specification of the WDTM.WDM1 and
WDTM.WDM0 bits. The INTWDT or WDTRES signal is also generated if the same value is written to the register.
The operation is not guaranteed if the register is written three or more times.
After this, the operation of the watchdog timer cannot be stopped.
10.5 Caution
can be calculated from “Interval time set to WDTM register + 2
successively without the watchdog timer being cleared.
started is not included.
(2) Watchdog timer enable register (WDTE)
The watchdog timer is stopped after reset is released.
The WDTM register can be written only once after reset is released. If the register is written a second time after
To use the watchdog timer, write the operation mode and the interval time to the WDTM register in 8-bit units.
To not use the watchdog timer, write 00H to the WDTM register.
The cycle of the non-maskable interrupt request signal (INTWDT) that is generated due to watchdog timer overflow
Note that the pulse width until generation of the first interrupt request signal after the watchdog timer has been
Cautions 1. If “ACH” is written to the WDTE register to enable the watchdog timer operation and then a
The counter of the watchdog timer is cleared and counting restarted by writing “ACH” to the WDTE register.
The WDTE register can be read or written in 8-bit units.
Reset sets this register to 1AH.
2. When the WDTE register is read or written in 1-bit units, an internal reset signal is output.
3. The read value of the WDTE register is “1AH” before the watchdog timer operates, and
WDTE
After reset: 1AH
value other than “ACH” is written to the WDTE register, a non-maskable interrupt request
signal (INTWDT) or a reset signal (WDTRES) is generated due to watchdog timer overflow,
depending on the specification of the WDTM.WDM1 and WDTM.WDM0 bits.
“9AH” after it operates. The value read from this register is different from the written value
(ACH).
CHAPTER 10 WATCHDOG TIMER FUNCTIONS
R/W
Address: FFFFF6D1H
User’s Manual U17716EJ2V0UD
7
peripheral clock pulse width”, if INTWDT occurs
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