UPD70F3714GC-8BS-A Renesas Electronics America, UPD70F3714GC-8BS-A Datasheet - Page 309

• Manufacturer Part Number: UPD70F3714GC-8BS-A
• Description: MCU 32BIT V850ES/LX2 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Ix2r

Specifications of UPD70F3714GC-8BS-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, UART/USART
• Peripherals: LVD, PWM, WDT
• Number Of I /o: 39
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

16-bit counter is cleared from FFFFH to 0000H, starts counting, and outputs a one-shot pulse from the TOQ0b pin.
After the one-shot pulse is output, the 16-bit counter is cleared to 0000H, stops counting, and waits for a trigger.
When the trigger is generated again, the 16-bit counter starts counting from 0000H. If a trigger is generated again
while the one-shot pulse is being output, it is ignored.
count value matches the value of the CCR0 buffer register. The compare match interrupt request signal INTTQ0CCb
is generated when the count value of the 16-bit counter matches the value of the CCRb buffer register.
TQ0CTL1
TQ0CTL0
When the TQ0CE bit is set to 1, 16-bit timer/event counter Q waits for a trigger. When the trigger is generated, the
The output delay period and active level width of the one-shot pulse can be calculated as follows.
The compare match interrupt request signal INTTQ0CC0 is generated when the 16-bit counter counts after its
Only setting the software trigger (TQ0CTL1.TQ0EST bit) to 1 is used as the trigger.
Remark
Output delay period = (Set value of TQ0CCRb register) × Count clock cycle
Active level width = (Set value of TQ0CCR0 register − Set value of TQ0CCRb register + 1) × Count clock cycle
(a) TMQ0 control register 0 (TQ0CTL0)
(b) TMQ0 control register 1 (TQ0CTL1)
Note The setting is invalid when the TQ0CTL1.TQ0EEE bit = 1.
b = 1 to 3
TQ0CE
0/1
0
TQ0EST
Figure 7-28. Register Setting in One-Shot Pulse Output Mode (1/3)
0/1
0
CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ)
TQ0EEE
0/1
0
0
0
User’s Manual U17716EJ2V0UD
0
0
TQ0CKS2 TQ0CKS1 TQ0CKS0
TQ0MD2 TQ0MD1 TQ0MD0
0/1
0
0/1
1
0/1
1
0, 1, 1:
One-shot pulse output mode
0: Operate on count clock
1: Count external event
Generate software trigger
when 1 is written
Select count clock
0: Stop counting
1: Enable counting
selected by TQ0CKS0 to
TQ0CKS2 bits
input signal
Note
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