MC9S12XD256VAG Freescale Semiconductor, MC9S12XD256VAG Datasheet - Page 169

• Manufacturer Part Number: MC9S12XD256VAG
• Description: IC MCU 256K FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XD256VAG

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 119
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 14K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5.3.2.4
This register controls the conversion sequence length, FIFO for results registers and behavior in freeze
mode. Writes to this register will abort current conversion sequence but will not start a new sequence.
Read: Anytime
Write: Anytime
Freescale Semiconductor
S8C, S4C,
S2C, S1C
Reset
ASCIE
ASCIF
Field
Field
6–3
1
0
W
R
Conversion Sequence Length — These bits control the number of conversions per sequence.
all combinations. At reset, S4C is set to 1 (sequence length is 4). This is to maintain software continuity to HC12
Family.
ATD Control Register 3 (ATDCTL3)
0
0
7
ATD Sequence Complete Interrupt Enable
0 ATD Sequence Complete interrupt requests are disabled.
1 ATD Interrupt will be requested whenever ASCIF = 1 is set.
ATD Sequence Complete Interrupt Flag — If ASCIE = 1 the ASCIF flag equals the SCF flag (see
Section 5.3.2.7, “ATD Status Register 0
0 No ATD interrupt occurred
1 ATD sequence complete interrupt pending
= Unimplemented or Reserved
S8C
0
6
ETRIGLE
Table 5-5. ATDCTL2 Field Descriptions (continued)
Figure 5-6. ATD Control Register 3 (ATDCTL3)
0
0
1
1
Table 5-6. External Trigger Configurations
Table 5-7. ATDCTL3 Field Descriptions
MC9S12XDP512 Data Sheet, Rev. 2.21
S4C
0
5
ETRIGP
0
1
0
1
(ATDSTAT0)”), else ASCIF reads zero. Writes have no effect.
S2C
0
4
Description
Description
External Trigger Sensitivity
Chapter 5 Analog-to-Digital Converter (S12ATD10B8CV2)
S1C
0
3
Falling edge
Rising edge
High level
Low level
FIFO
0
2
FRZ1
0
1
Table 5-8
FRZ0
0
0
shows
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