MC9S12XD256VAG Freescale Semiconductor, MC9S12XD256VAG Datasheet - Page 596
MC9S12XD256VAG
Manufacturer Part Number
MC9S12XD256VAG
Description
IC MCU 256K FLASH 144-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet
1.MC9S12XD64CAA.pdf
(1348 pages)
Specifications of MC9S12XD256VAG
Core Processor
HCS12X
Core Size
16-Bit
Speed
80MHz
Connectivity
CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
119
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
14K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 5.5 V
Data Converters
A/D 24x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 105°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Chapter 16 Interrupt (S12XINTV1)
16.1.1
The following terms and abbreviations are used in the document.
16.1.2
16.1.3
1. The vector base is a 16-bit address which is accumulated from the contents of the interrupt vector base register (IVBR, used
2. The IRQ interrupt can only be handled by the CPU
596
as upper byte) and 0x00 (used as lower byte).
•
•
•
•
•
•
•
•
•
•
•
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Interrupt vector base register (IVBR)
One spurious interrupt vector (at address vector base
2–113 I bit maskable interrupt vector requests (at addresses vector base + 0x0012–0x00F2).
Each I bit maskable interrupt request has a configurable priority level and can be configured to be
handled by either the CPU or the XGATE module
I bit maskable interrupts can be nested, depending on their priority levels.
One X bit maskable interrupt vector request (at address vector base + 0x00F4).
One non-maskable software interrupt request (SWI) or background debug mode vector request (at
address vector base + 0x00F6).
One non-maskable unimplemented opcode trap (TRAP) vector (at address vector base + 0x00F8).
Three system reset vectors (at addresses 0xFFFA–0xFFFE).
Determines the highest priority DMA and interrupt vector requests, drives the vector to the XGATE
module or to the bus on CPU request, respectively.
Wakes up the system from stop or wait mode when an appropriate interrupt request occurs or
whenever XIRQ is asserted, even if X interrupt is masked.
XGATE can wake up and execute code, even with the CPU remaining in stop or wait mode.
Run mode
This is the basic mode of operation.
Glossary
Features
Modes of Operation
XGATE
Term
XIRQ
DMA
MCU
CCR
IRQ
ISR
INT
IPL
Condition Code Register (in the S12X CPU)
Direct Memory Access
Interrupt
Interrupt Processing Level
Interrupt Service Routine
Micro-Controller Unit
please refer to the "XGATE Block Guide"
refers to the interrupt request associated with the IRQ pin
refers to the interrupt request associated with the XIRQ pin
MC9S12XDP512 Data Sheet, Rev. 2.21
Table 16-1. Terminology
2
Meaning
.
1
+ 0x0010).
Freescale Semiconductor
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