MC9S12XD256VAG Freescale Semiconductor, MC9S12XD256VAG Datasheet - Page 716

• Manufacturer Part Number: MC9S12XD256VAG
• Description: IC MCU 256K FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XD256VAG

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 119
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 14K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 19 S12X Debug (S12XDBGV2) Module
19.4.2.3.2
In the outside range comparator mode, either comparator pair A and B or comparator pair C and D can be
configured for range comparisons. A single match condition on either of the comparators is recognized as
valid. An aligned word access which straddles the range boundary will cause a trigger only if the aligned
address is outside the range.
Outside range mode in combination with tagged triggers can be used to detect if the opcode fetches are
from an unexpected range. In forced trigger modes the outside range trigger would typically be activated
at any interrupt vector fetch or register access. This can be avoided by setting the upper range limit to
0x7FFFFF or lower range limit to 0x000000 respectively.
When comparing the XGATE address bus in outside range mode, the initial vector fetch as determined by
the vector contained in the XGATE XGVBR register should be taken into consideration. The XGVBR
register and hence vector address can be modified.
19.4.3
Trigger modes are used as qualifiers for a state sequencer change of state. The control logic determines the
trigger mode and provides a trigger to the state sequencer. The individual trigger modes are described in
the following sections.
19.4.3.1
If a comparator match occurs, a trigger occurs to initiate a transition to another state sequencer state and
the corresponding flags in DBGSR are set. For a comparator match to trigger firstly the comparator must
be enabled by setting the COMPE bit in the corresponding comparator control register. Secondly the state
control register for the current state must enable the match for that state. The state control registers allow
for different matches to be enabled in each of the states 1 to 3.
19.4.3.2
If either a CPU or XGATE taghit occurs a transition to another state sequencer state is initiated and the
corresponding DBGSR flags are set. For a comparator related taghit to occur, the DBG must first generate
tags based on comparator matches. When the tagged instruction reaches the execution stage of the
instruction queue a taghit is generated by the CPU/XGATE.
19.4.3.3
In external tagging trigger mode, the TAGLO and TAGHI pins (mapped to device pins) are used to tag an
instruction. This function can be used as another breakpoint source. When the tagged opcode reaches the
execution stage of the instruction queue a transition to the disarmed state0 occurs, ending the debug session
and generating a breakpoint, if breakpoints are enabled. External tagging is only possible in device
emulation modes.
718
Trigger Modes
Trigger On Comparator Match
Trigger On Comparator Related Taghit
External Tag Trigger
Outside Range (Address < CompAC_Addr or Address > CompBD_Addr)
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor