MC9S12XD256VAG Freescale Semiconductor, MC9S12XD256VAG Datasheet - Page 831

• Manufacturer Part Number: MC9S12XD256VAG
• Description: IC MCU 256K FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XD256VAG

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 119
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 14K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

22.3.2.10 Port E Data Direction Register (DDRE)
Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other
modes the data are read from this register.
Write: Anytime. In emulation modes, write operations will also be directed to the external bus.
Freescale Semiconductor
DDRE[7:2]
Reset
Field
7–0
W
R
DDRE7
Data Direction Port E — his register controls the data direction for port E. When Port E is operating as a general
purpose I/O port, DDRE determines whether each pin is an input or output. A logic level “1” causes the
associated port pin to be an output and a logic level “0” causes the associated pin to be a high-impedance input.
Port E bit 1 (associated with IRQ) and bit 0 (associated with XIRQ) cannot be configured as outputs. Port E, bits
1 and 0, can be read regardless of whether the alternate interrupt function is enabled.
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read
0
7
on PORTE after changing the DDRE register.
= Unimplemented or Reserved
DDRE6
0
6
Figure 22-12. Port E Data Direction Register (DDRE)
Table 22-13. DDRE Field Descriptions
DDRE5
MC9S12XDP512 Data Sheet, Rev. 2.21
0
5
DDRE4
0
4
Description
Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2)
DDRE3
0
3
DDRE2
0
2
0
0
1
0
0
0
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