MCF5280CVM66 Freescale Semiconductor, MCF5280CVM66 Datasheet - Page 325

• Manufacturer Part Number: MCF5280CVM66
• Description: IC MPU 32BIT COLDF 256-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF528xr

Specifications of MCF5280CVM66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 142
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Controller Family/series: ColdFire
• No. Of I/o's: 150
• Program Memory Size: 2KB
• Ram Memory Size: 64KB
• Cpu Speed: 66.67MHz
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of Pwm Channels: 8
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

17.4.8
The MSCR provides control of the MII clock (FEC_MDC pin) frequency and allows a preamble drop on
the MII management frame.
The MII_SPEED field must be programmed with a value to provide an FEC_MDC frequency of less than
or equal to 2.5 MHz to be compliant with the IEEE 802.3 MII specification. The MII_SPEED must be set
to a non-zero value to source a read or write management frame. After the management frame is complete,
the MSCR register may optionally be set to 0 to turn off the FEC_MDC. The FEC_MDC generated has a
50% duty cycle except when MII_SPEED changes during operation (change takes effect following a rising
or falling edge of FEC_MDC).
If the internal bus clock is 25 MHz, programming this register to 0x0000_0005 results in an FEC_MDC
as stated the equation below.
A table showing optimum values for MII_SPEED as a function of internal bus clock frequency is provided
below.
Freescale Semiconductor
MII_SPEED
DIS_PRE
Field
31–8
6–1
7
0
IPSBAR
Offset:
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIS_
Reserved, must be cleared.
Setting this bit causes the preamble (32 ones) not to be prepended to the MII management frame. The MII
standard allows the preamble to be dropped if the attached PHY device(s) does not require it.
Controls the frequency of the MII management interface clock (FEC_MDC) relative to the internal bus clock. A
value of 0 in this field turns off the FEC_MDC and leaves it in low voltage state. Any non-zero value results in the
FEC_MDC frequency of 1/(MII_SPEED × 2) of the internal bus frequency.
Reserved, must be cleared.
MII Speed Control Register (MSCR)
0x1044
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Internal FEC Clock
Frequency
25 MHz
33 MHz
40 MHz
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Figure 17-8. MII Speed Control Register (MSCR)
Table 17-12. Programming Examples for MSCR
Table 17-11. MSCR Field Descriptions
25 MHz
×
MSCR[MII_SPEED]
----------- -
5
×
1
2
=
0x7
0x8
0x5
2.5 MHz
Description
FEC_MDC frequency
2.50 MHz
2.36 MHz
2.50 MHz
8
PRE
0
7
Access: User read/write
Fast Ethernet Controller (FEC)
0 0 0 0 0 0 0
6
MII_SPEED
5
4
3
2
Eqn. 17-1
1
0
0
17-15