MCF5280CVM66 Freescale Semiconductor, MCF5280CVM66 Datasheet - Page 621

• Manufacturer Part Number: MCF5280CVM66
• Description: IC MPU 32BIT COLDF 256-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF528xr

Specifications of MCF5280CVM66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 142
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Controller Family/series: ColdFire
• No. Of I/o's: 150
• Program Memory Size: 2KB
• Ram Memory Size: 64KB
• Cpu Speed: 66.67MHz
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of Pwm Channels: 8
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

branch target address calculation is based on the contents of a program-visible register (variant
addressing). DDATA outputs can be configured to display the target address of such instructions in
sequential nibble increments across multiple processor clock cycles, as described in
“Begin Execution of Taken Branch (PST =
connecting the processor’s high-speed local bus to the external development system through PST[3:0] and
DDATA[3:0]. The buffer captures branch target addresses and certain data values for eventual display on
the DDATA port, one nibble at a time starting with the least significant bit (lsb).
Execution speed is affected only when both storage elements contain valid data to be dumped to the
DDATA port. The core stalls until one FIFO entry is available.
Table 30-2
Freescale Semiconductor
0x8–
Hex
0xC
0xD
0xB
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
PST[3:0]
Binary
1000–
0000
0001
0010
0011
0100
0101
0110
0111
1011
1100
1101
shows the encoding of these signals.
Continue execution. Many instructions execute in one processor cycle. If an instruction requires more
processor clock cycles, subsequent clock cycles are indicated by driving PST outputs with this encoding.
Begin execution of one instruction. For most instructions, this encoding signals the first processor clock
cycle of an instruction’s execution. Certain change-of-flow opcodes, plus the PULSE and WDDATA
instructions, generate different encodings.
Reserved
Entry into user-mode. Signaled after execution of the instruction that caused the ColdFire processor to
enter user mode.
Begin execution of PULSE and WDDATA instructions. PULSE defines logic analyzer triggers for debug
and/or performance analysis. WDDATA lets the core write any operand (byte, word, or longword) directly
to the DDATA port, independent of debug module configuration. When WDDATA is executed, a value of
0x4 is signaled on the PST port, followed by the appropriate marker, and then the data transfer on the
DDATA port. Transfer length depends on the WDDATA operand size.
Begin execution of taken branch. For some opcodes, a branch target address may be displayed on
DDATA depending on the CSR settings. CSR also controls the number of address bytes displayed,
indicated by the PST marker value preceding the DDATA nibble that begins the data output. See
Section 30.3.1, “Begin Execution of Taken Branch (PST =
Reserved
Begin execution of return from exception (RTE) instruction.
Indicates the number of bytes to be displayed on the DDATA port on subsequent processor clock cycles.
The value is driven onto the PST port one CLKOUT cycle before the data is displayed on DDATA.
0x8 Begin 1-byte transfer on DDATA.
0x9 Begin 2-byte transfer on DDATA.
0xA Begin 3-byte transfer on DDATA.
0xB Begin 4-byte transfer on DDATA.
Exception processing. Exceptions that enter emulation mode (debug interrupt or optionally trace)
generate a different encoding, as described below. Because the 0xC encoding defines a multiple-cycle
mode, PST outputs are driven with 0xC until exception processing completes.
Entry into emulator mode. Displayed during emulation mode (debug interrupt or optionally trace).
Because this encoding defines a multiple-cycle mode, PST outputs are driven with 0xD until exception
processing completes.
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Table 30-2. Processor Status Encoding
0x5).” Two 32-bit storage elements form a FIFO buffer
Definition
0x5).”
Section 30.3.1,
Debug Support
30-3