MCF5280CVM66 Freescale Semiconductor, MCF5280CVM66 Datasheet - Page 610

• Manufacturer Part Number: MCF5280CVM66
• Description: IC MPU 32BIT COLDF 256-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF528xr

Specifications of MCF5280CVM66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 142
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Controller Family/series: ColdFire
• No. Of I/o's: 150
• Program Memory Size: 2KB
• Ram Memory Size: 64KB
• Cpu Speed: 66.67MHz
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of Pwm Channels: 8
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Reset Controller Module
29.3
Table 29-1
following paragraphs.
29.3.1
Asserting the external RSTI for at least four rising CLKOUT edges causes the external reset request to be
recognized and latched.
29.3.2
This active-low output signal is driven low when the internal reset controller module resets the chip. When
RSTO is active, the user can drive override options on the data bus.
29.4
The reset controller programming model consists of these registers:
See
29-2
•
•
Table 29-2
Reset control register (RCR), which selects reset controller functions
Reset status register (RSR), which reflects the state of the last reset source
Signals
Memory Map and Registers
provides a summary of the reset controller signal properties. The signals are described in the
RSTI
RSTO
1
RSTI
RSTO
RSTI is always synchronized except when in low-power stop mode.
for the memory map and the following paragraphs for a description of the registers.
Name
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Timer Timeout
Loss of Clock
Loss of Lock
Power-On
Watchdog
Software
Detect
Table 29-1. Reset Controller Signal Properties
Reset
Reset
LVD
PLL
PLL
Figure 29-1. Reset Controller Block Diagram
RSTI
Pin
Direction
O
I
Controller
Reset
Hysteresis
Input
—
Y
To Internal Resets
RSTO
Pin
Synchronization
Input
Y
—
1
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