MCF5280CVM66 Freescale Semiconductor, MCF5280CVM66 Datasheet - Page 633

• Manufacturer Part Number: MCF5280CVM66
• Description: IC MPU 32BIT COLDF 256-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF528xr

Specifications of MCF5280CVM66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 142
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Controller Family/series: ColdFire
• No. Of I/o's: 150
• Program Memory Size: 2KB
• Ram Memory Size: 64KB
• Cpu Speed: 66.67MHz
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of Pwm Channels: 8
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

A write to TDR clears the CSR trigger status bits, CSR[BSTAT].
Table 30-14
Freescale Semiconductor
DRc[4–0]
31–30
15–14
29/13
Bits
Reset
Reset
Field
Field
R/W Write only. Accessible in supervisor mode as debug control register 0x07 using the WDEBUG instruction and
through the BDM port using the
Name
31
15
describes TDR fields.
TRC
EBL
LxT
TRC
LxT
The debug module has no hardware interlocks, so to prevent spurious
breakpoint triggers while the breakpoint registers are being loaded, disable
TDR (by clearing TDR[29,13]) before defining triggers.
30
14
Trigger response control. Determines how the processor responds to a completed trigger condition.
The trigger response is always displayed on DDATA.
00 Display on DDATA only
01 Processor halt
10 Debug interrupt
11 Reserved
Level-x trigger. This is a Rev. B function only. The Level-x Trigger bit determines the logic operation
for the trigger between the PC_condition and the (Address_range & Data_condition) where the
inclusion of a Data condition is optional. The ColdFire debug architecture supports the creation of
single or double-level triggers.
TDR[15]
0 Level-2 trigger = PC_condition & Address_range & Data_condition
1 Level-2 trigger = PC_condition | (Address_range & Data_condition)
TDR[14]
0 Level-1 trigger = PC_condition & Address_range & Data_condition
1 Level-1 trigger = PC_condition | (Address_range & Data_condition)
Enable breakpoint. Global enable for the breakpoint trigger. Setting TDR[EBL] enables a breakpoint
trigger. Clearing it disables all breakpoints at that level.
EBL
EBL
29
13
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
EDLW EDWL EDWU EDLL EDLM EDUM EDUU
EDLW EDWL EDWU EDLL EDLM EDUM EDUU
28
12
Figure 30-11. Trigger Definition Register (TDR)
27
11
Table 30-14. TDR Field Descriptions
WDMREG
26
10
command.
25
0000_0000_0000_0000
0000_0000_0000_0000
9
NOTE
Second-Level Trigger
24
First-Level Trigger
8
Description
0x07
23
7
22
6
DI
DI
21
5
EAI EAR EAL EPC PCI
EAI EAR EAL EPC PCI
20
4
19
3
18
2
Debug Support
17
1
16
0
30-15