WG82574L S LBA9 Intel, WG82574L S LBA9 Datasheet - Page 144

• Manufacturer Part Number: WG82574L S LBA9
• Description: CONTROLLER, ENET, INTEL 82574L, 64PQFN
• Manufacturer: Intel

Specifications of WG82574L S LBA9

• Ethernet Type: IEEE 802.3, IEEE 802.3u, IEEE 802.3ab
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: 0°C To +85°C
• Digital Ic Case Style: QFN
• No. Of Pins: 64
• Package / Case: QFN
• Interface Type: I2C, JTAG, PCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.1.9
144
Receive Interrupts
The following indicates the presence of new packets:
A predetermined amount of time has elapsed since the last packet was received and
transferred to host memory. Every time a new packet is received and transferred to the
host memory, the timer is re-initialized to the predetermined value. The timer then
counts down and triggers an interrupt if no new packet is received and transferred to
host memory completely before the timer expires. Software can set the timer value to
zero if it needs to be notified immediately (no interval delay) whenever a new packet
has been stored in memory.
Writing the absolute timer with its high order bit set to 1b forces an explicit flush of any
partial cache lines worth of consumed descriptors. Hardware writes all used descriptors
to memory and updates the globally visible value of the RXDH head pointer(s).
This timer is re-initialized when an interrupt is generated and restarts when a new
packet is observed. It stays disabled until a new packet is received and transferred to
the host memory. The packet delay timer is also re-initialized when an interrupt occurs
due to an absolute timer expiration or small packet-detection interrupt.
A predetermined amount of time has elapsed since the first packet received after the
hardware timer was written (specifically, after the last packet data byte was written to
memory).
This timer is re-initialized when an interrupt is generated and restarts when a new
packet is observed. It stays disabled until a new packet is received and transferred to
the host memory. The absolute delay timer is also re-initialized when an interrupt
occurs due to a packet timer expiration or small packet-detection interrupt.
The absolute timer and the packet delay timer can be used together. The following
table lists the conditions when the absolute timer and the packet delay timer are
initialized, disabled and when they start counting. The timer is always disabled if the
value of the RDTR = 0b.
Figure 31
Absolute delay
timer
Packet delay
timer
• Receive Timer (ICR.RXT0) due to packet delay timer (RDTR)
• Receive Timer (ICR.RXT0) due to absolute timer (RADV)
Interrupt
Timers
further clarifies the packet timer operation.
Timer inactive and
receive packet
transferred to host
memory.
Timer inactive and
receive packet
transferred to host
memory.
When Starts
Counting
At start
At start
New packet received and
transferred to host memory
When Re-initialized
82574 GbE Controller—Inline Functions
On expiration
Due to other receive
interrupt.
On expiration
Due to other receive
interrupt.
When Disabled