WG82574L S LBA9 Intel, WG82574L S LBA9 Datasheet - Page 286

• Manufacturer Part Number: WG82574L S LBA9
• Description: CONTROLLER, ENET, INTEL 82574L, 64PQFN
• Manufacturer: Intel

Specifications of WG82574L S LBA9

• Ethernet Type: IEEE 802.3, IEEE 802.3u, IEEE 802.3ab
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: 0°C To +85°C
• Digital Ic Case Style: QFN
• No. Of Pins: 64
• Package / Case: QFN
• Interface Type: I2C, JTAG, PCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10.1.3
Note:
Note:
Note:
10.2
10.2.1
286
Register Conventions
All registers in the 82574 are defined to be 32 bits. They should be accessed as 32-bit
double-words. There are some exceptions to this rule:
Reserved bit positions: Some registers contain certain bits that are marked as
reserved.
Reads from registers containing reserved bits might return indeterminate values in the
reserved bit-positions unless read values are explicitly stated. When read, these
reserved bits should be ignored by software.
Reserved and/or undefined addresses: any register address not explicitly declared
in this specification should be considered to be reserved, and should not be written to.
Writing to reserved or undefined register addresses can cause indeterminate behavior.
Reads from reserved or undefined configuration register addresses might return
indeterminate values unless read values are explicitly stated for specific addresses.
Initial values: most registers define the initial hardware values prior to being
programmed. In some cases, hardware initial values are undefined and are listed as
such via the text undefined, unknown, or X. Some of these configuration values should
be set via NVM configuration or via software in order to insure proper operation. This
need is dependent on the function of the bit. Other registers might cite a hardware
default which is overridden by a higher-precedence operation. Operations that might
supersede hardware defaults can include:
For registers that should be accessed as 32-bit double words, partial writes (less than a
32-bit double word) does not take effect (such as, the write is ignored).
return all 32 bits of data regardless of the byte enables.
Partial reads to clear-by-read registers (such as, ICR) can have unexpected results
since all 32 bits are actually read regardless of the byte enables. Partial reads should
not be done.
All statistics registers are implemented as 32-bit registers. Though some logical
statistics registers represent counters in excess of 32-bits in width, registers must be
accessed using 32-bit operations (such as, independent access to each 32-bit field).
See special notes for VLAN Filter table and multicast table arrays in their specific
register definitions.
Configuration and Status Registers - CSR Space
Register Summary Table
All registers are listed in
not necessarily listed in the order that they appear in the address space.
• Register pairs where two 32-bit registers make up a larger logical size.
• Accesses to Flash memory (via expansion ROM space, secondary BAR space, or the
• A valid NVM load
• Completion of a hardware operation (such as hardware auto-negotiation)
• Writing of a different register whose value is then reflected in another bit
I/O space) can be byte, word or double word accesses.
Section
79. These registers are ordered by grouping and are
82574 GbE Controller—Driver Programing Interface
Partial reads