WG82574L S LBA9 Intel, WG82574L S LBA9 Datasheet - Page 301

• Manufacturer Part Number: WG82574L S LBA9
• Description: CONTROLLER, ENET, INTEL 82574L, 64PQFN
• Manufacturer: Intel

Specifications of WG82574L S LBA9

• Ethernet Type: IEEE 802.3, IEEE 802.3u, IEEE 802.3ab
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: 0°C To +85°C
• Digital Ic Case Style: QFN
• No. Of Pins: 64
• Package / Case: QFN
• Interface Type: I2C, JTAG, PCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Driver Programing Interface—82574 GbE Controller
Note:
Note:
Note:
10.2.2.6
This register provides extended control of device functionality beyond that provided by
the Device Control (CTRL) register.
Device Control register values are changed by a read of the EEPROM which occurs upon
assertion of the EE_RST bit. Therefore, if software uses the EE_RST function and
desires to retain current configuration information, the contents of the control registers
should be read and stored by software.
The EEPROM reset function might read configuration information out of the EEPROM
which affects the configuration of PCIe configuration space BAR settings. The changes
to the BARs are not visible unless the system is rebooted and the BIOS is allowed to re-
map them.
The SPD_BYPS bit performs a similar function to the CTRL.FRCSPD bit in that the
device's speed settings are determined by the value software writes to the CRTL.SPEED
bits. However, with the SPD_BYPS bit asserted, the settings in CTRL.SPEED take effect
rather than waiting until after the device's clock switching circuitry performs the
change.
Flash Access Register - FLA (0x0001C; RW)
FL_NVM_SK
FL_CE
FL_SI
FL_SO
FL_REQ
FL_GNT
FL_DEV_ER_IND
FL_SEC_ER_IND
FL_WR_IND
SW_WR_DONE
Field
1
1
2
3
4
5
6
7
8
9
0
Bit(s)
0b
0b
0b
X
0b
0b
0b
0b
0b
1b
Initial
Value
Clock input to the FLASH
When FL_GNT is 1, the FL_NVM_SK output signal is mapped to
this bit and provides the serial clock input to the Flash. Software
clocks the Flash via toggling this bit with successive writes.
Chip select input to the FLASH
When FL_GNT is 1, the FL_CE output signal is mapped to the chip
select of the FLASH device. Software enables the FLASH by
writing a 0 to this bit.
Data input to the FLASH
When FL_GNT is 1, the FL_SI output signal is mapped directly to
this bit. Software provides data input to the FLASH via writes to
this bit.
Data output bit from the FLASH
The FL_SO input signal is mapped directly to this bit in the
register and contains the Flash serial data output. This bit is read-
only from the software perspective – writes to this bit have no
effect.
Request FLASH Access
The software must write a 1 to this bit to get direct Flash access.
It has access when FL_GNT is 1. When the software completes
the access it must write a 0.
Grant FLASH Access
When this bit is set to 1b, the software can access the Flash using
the SK, CS, DI, and DO bits.
Status Bit
Indicates manageability initiated a device erase transaction to the
Flash.
Status Bit
Indicates manageability initiated a sector erase transaction to the
Flash.
Status Bit
Indicates manageability initiated a write transaction to the Flash.
Status Bit
Indicates that last LAN_BAR or LAN_EXP write was done.
Description
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