WG82574L S LBA9 Intel, WG82574L S LBA9 Datasheet - Page 446
WG82574L S LBA9
Manufacturer Part Number
WG82574L S LBA9
Description
CONTROLLER, ENET, INTEL 82574L, 64PQFN
Manufacturer
Intel
Datasheet
1.WG82574IT_S_LBAC.pdf
(490 pages)
Specifications of WG82574L S LBA9
Ethernet Type
IEEE 802.3, IEEE 802.3u, IEEE 802.3ab
Supply Voltage Range
3V To 3.6V
Operating Temperature Range
0°C To +85°C
Digital Ic Case Style
QFN
No. Of Pins
64
Package / Case
QFN
Interface Type
I2C, JTAG, PCI, SPI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Figure 73.
13.5.5
13.5.5.1
446
82574L 10/100 Mb/s Magnetics Module Connections (With CMC)
Layout Considerations for the Ethernet Interface
These sections provide recommendations for performing printed circuit board layouts.
Good layout practices are essential to meet IEEE PHY conformance specifications and
EMI regulatory requirements.
Critical signal traces should be kept as short as possible to decrease the likelihood of
being affected by high frequency noise from other signals, including noise carried on
power and ground planes. Keeping the traces as short as possible can also reduce
capacitive loading.
Since the transmission line medium extends onto the printed circuit board, special
attention must be paid to layout and routing of the differential signal pairs.
Designing for 1000 BASE-T Gigabit operation is very similar to designing for 10 and 100
Mb/s. For the 82574, system level tests should be performed at all three speeds.
Guidelines for Component Placement
Component placement can affect signal quality, emissions, and component operating
temperature This section provides guidelines for component placement.
Careful component placement can:
M o d u le w ith C o m m o n M o d e
• Decrease potential problems directly related to electromagnetic interference (EMI),
• Simplify the task of routing traces. To some extent, component orientation will
C h o ke in B o th R x a n d T x
which could cause failure to meet applicable government test specifications.
affect the complexity of trace routing. The overall objective is to minimize turns and
crossovers between traces.
1 0 /1 0 0 M a g n e tics
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M D I_ M IN U S (0 )
M D I_ M IN U S (1 )
M D I_ M IN U S (2 )
M D I_ M IN U S (3 )
R e s is to rs
50 O h m
82574 GbE Controller—Design Considerations
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