WG82574L S LBA9 Intel, WG82574L S LBA9 Datasheet - Page 150

• Manufacturer Part Number: WG82574L S LBA9
• Description: CONTROLLER, ENET, INTEL 82574L, 64PQFN
• Manufacturer: Intel

Specifications of WG82574L S LBA9

• Ethernet Type: IEEE 802.3, IEEE 802.3u, IEEE 802.3ab
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: 0°C To +85°C
• Digital Ic Case Style: QFN
• No. Of Pins: 64
• Package / Case: QFN
• Interface Type: I2C, JTAG, PCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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However, RSS is the only usage that is described specifically. Other uses should make
use of the available hardware.
Multiple receive queues are enabled when the RXCSUM.PCSD bit is set (packet
checksum is disabled) and the Multiple Receive Queues Enable bits are not 00b.
Multiple receive queues are therefore mutually exclusive with UDP fragmentation, and
is unsupported when using legacy receive descriptor format; multiple receive queue
status is not reported in the receive packet descriptor, and the interrupt mechanism
bypasses the interrupt scheme described in
issued directly to the interrupt logic.
When multiple receive queues are enabled, the 82574 provides software with several
types of information. Some are requirements of Microsoft* RSS while others are
provided for software device driver assistance:
Figure 33
When multiple requests queues are disabled, packets enter hardware queue 0. System
software might enable or disable RSS at any time. While disabled, system software
might update the contents of any of the RSS-related registers.
When multiple request queues are enabled in RSS mode, undecodable packets enter
hardware queue 0. The 32-bit tag (normally a result of the hash function) equals zero.
The 5-bit MRQ field equals zero as well.
1. The receive packet is parsed into the header fields used by the hash operation
2. A hash calculation is performed. The 82574L supports a single hash function, as
3. The seven LSBs of the hash result are used as an index into a 128-entries
• A Dword result of the Microsoft* RSS hash function, to be used by the stack for
• A 4-bit RSS Type field conveys the hash function used for the specific packet
• A mechanism to issue an interrupt to one or more CPUs
flow classification, is written into the receive packet descriptor (required by
Microsoft* RSS).
(required by Microsoft* RSS).
(such as, IP addresses, TCP port, etc.).
defined by Microsoft* RSS. The 82574L therefore does not indicate to the software
device driver which hash function is used. The 32-bit result is fed into the packet
receive descriptor.
redirection table. Each entry in the table contains a 5-bit CPU number. This 5-bit
value is fed into the packet receive descriptor. In addition, each entry provides a
single bit queue number, which denotes that queue into which the packet is routed.
shows the process of classifying a packet into a receive queue:
section
7.1.11. Instead, a receive packet is
82574 GbE Controller—Inline Functions
(section
7.1.11).