WG82574L S LBA9 Intel, WG82574L S LBA9 Datasheet - Page 180

• Manufacturer Part Number: WG82574L S LBA9
• Description: CONTROLLER, ENET, INTEL 82574L, 64PQFN
• Manufacturer: Intel

Specifications of WG82574L S LBA9

• Ethernet Type: IEEE 802.3, IEEE 802.3u, IEEE 802.3ab
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: 0°C To +85°C
• Digital Ic Case Style: QFN
• No. Of Pins: 64
• Package / Case: QFN
• Interface Type: I2C, JTAG, PCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.4
7.4.1
7.4.2
180
UDP Header
Interrupts
The 82574L supports the following interrupt modes:
Legacy and MSI Interrupt Modes
In legacy and MSI modes, an interrupt cause is reflected by setting one of the bits in
the ICR register, where each bit reflects one or more causes. This description of ICR
register provides the mapping of interrupt causes (for example, a specific Rx queue
event or a LSC event) to bits in the ICR.
Mapping of causes relating to the Tx and Rx queues as well as non-queue causes in this
mode is not configurable. Each possible queue interrupt cause (such as, each Rx
queue, Tx queue or any other interrupt source) has an entry in the ICR.
The following configuration and parameters are involved:
MSI-X Mode
MSI-X defines a separate optional extension to basic MSI functionality. Compared to
MSI, MSI-X supports a larger maximum number of vectors per function, the ability for
software to control aliasing when fewer vectors are allocated than requested, plus the
ability for each vector to use an independent address and data value, is specified by a
table that resides in Memory Space. However, most of the other characteristics of MSI-
X are identical to those of MSI. For more information on MSI-X, refer to the PCI Local
Bus Specification, Revision 3.0.
In MSI-X mode, an interrupt cause is mapped into an MSI-X vector. This section
describes the mapping of interrupt causes (for example, a specific Rx queue event or a
LSC event) to MSI-X vectors.
Mapping is accomplished through the IVAR register. Each possible cause for an
interrupt is allocated an entry in the IVAR, and each entry in the IVAR identifies one
MSI-X vector. It is possible to map multiple interrupt causes into the MSI-X vector.
Interrupt causes that are not related to the Tx and Rx queues are also mapped via the
IVAR register.
The ICR also reflects interrupt causes related to non-queue causes. These are mapped
directly into the ICR (as in the legacy case), with each cause allocated a separate bit.
• UDP length: (last frame payload bytes + HDRLEN) - TUCSS
• UDP Checksum
• PCI legacy interrupts
• PCI MSI - Message Signaled Interrupts
• PCI MSI-X - Extended Message Signaled Interrupts
• The ICR[31:0] bits are allocated to specific interrupt causes
82574 GbE Controller—Inline Functions