WG82574L S LBA9 Intel, WG82574L S LBA9 Datasheet - Page 268

• Manufacturer Part Number: WG82574L S LBA9
• Description: CONTROLLER, ENET, INTEL 82574L, 64PQFN
• Manufacturer: Intel

Specifications of WG82574L S LBA9

• Ethernet Type: IEEE 802.3, IEEE 802.3u, IEEE 802.3ab
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: 0°C To +85°C
• Digital Ic Case Style: QFN
• No. Of Pins: 64
• Package / Case: QFN
• Interface Type: I2C, JTAG, PCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9.1.4.3
9.1.4.4
9.1.4.5
9.1.4.6
9.1.5
268
Message Control Offset 0xD2, (R/W)
The register fields are listed in the following table.
Message Address Low Offset 0xD4, (R/W)
Written by the system to indicate the lower 32 bits of the address to use for the MSI
memory write transaction. The lower two bits always returns 0b regardless of the write
operation.
Message Address High, Offset 0xD8, (R/W)
Written by the system to indicate the upper 32 bits of the address to use for the MSI
memory write transaction.
Message Data, Offset 0xDC, (R/W)
Written by the system to indicate the lower 16 bits of the data written in the MSI
memory write Dword transaction. The upper 16 bits of the transaction are written as
0b.
MSI-X Configuration
The MSI-X capability structure is listed in
both an MSI and an MSI-X capability structure.
In contrast to the MSI capability structure, which directly contains all of the control/
status information for the function's vectors, the MSI-X capability structure instead
points to an MSI-X table structure and a MSI-X Pending Bit Array (PBA) structure, each
residing in memory space.
Each structure is mapped by a BAR belonging to the 82574, located beginning at 0x10
in the configuration space. A BAR Indicator Register (BIR) indicates which BAR and a
Qword-aligned offset indicates where the structure begins relative to the base address
associated with the BAR. The BAR is permitted to be either 32-bit or 64-bit, but must
map memory space. The 82574L is permitted to map both structures with the same
BAR, or to map each structure with a different BAR.
The MSI-X table structure, detailed in
entries, each consisting of several fields: message address, message upper address,
message data, and vector control. Each entry is capable of specifying a unique vector.
The Pending Bit Array (PBA) structure, shown in the same section, contains the
function's pending bits, one per table entry, organized as a packed array of bits within
Qwords.
Bits
0
3:1
6:4
7
15:8
Default
0b
000b
000b
1b
0x0
R/W
R/W
RO
RO
RO
RO
Description
MSI Enable
If set to 1b, MSI. In this case, the 82574 generates MSI for interrupt assertion
instead of INTx signaling.
Multiple Message Capable
The 82574L indicates a single requested message.
Multiple Message Enable
The 82574L returns 000b to indicate that it supports a single message.
64-bit capable. A value of 1b indicates that the 82574 is capable of generating
64-bit message addresses.
Reserved, reads as 0b.
section 10.2.10
Table
72. The 82574L is permitted to have
82574 GbE Controller—Programing Interface
typically contains multiple