WG82574L S LBA9 Intel, WG82574L S LBA9 Datasheet - Page 386

• Manufacturer Part Number: WG82574L S LBA9
• Description: CONTROLLER, ENET, INTEL 82574L, 64PQFN
• Manufacturer: Intel

Specifications of WG82574L S LBA9

• Ethernet Type: IEEE 802.3, IEEE 802.3u, IEEE 802.3ab
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: 0°C To +85°C
• Digital Ic Case Style: QFN
• No. Of Pins: 64
• Package / Case: QFN
• Interface Type: I2C, JTAG, PCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

386
11
10
9
8
7
6
5:0
Bits
Power Down
Isolate
Restart
Copper
Auto-
Negotiation
Copper
Duplex
Mode
Collision
Test
Speed
Selection
(MSB)
Reserved
Field
R/W
RO
R/W,SC
RO
R/W
RO
R/W
Mode
See
Description
0x0
0x0
0x1
0x0
Always 0x0
0x1
HW Rst
Retain
0x0
SC
0x0
Update
Always
0x0
SW Rst
Update
82574 GbE Controller—Driver Programing Interface
Power down is controlled via register 0.11 and
16_0.2. Both bits must be set to 0b before the PHY
transitions from power down to normal operation.
When the port is switched from power down to
normal operation, a software reset and restart
auto-negotiation are performed even when bits
Reset (0_15) and Restart Auto-Negotiation (0.9)
are not set by the user. IEEE power down shuts
down the 82574 except for the GMII interface if
16_2.3 is set to 1b. If 16_2.3 is set to 0b, then the
GMII interface also shuts down. After a hardware
reset, this bit takes on the value of pd_pwrdn_a.
1b = Power down.
0b = Normal operation.
When pd_pwrdn_a transitions from 1b to 0b this
bit is set to 0b. When pd_pwrdn_a transitions from
0b to 1b this bit is set to 1b.
This bit has no effect.
When pd_aneg_now_a transitions from 0b to 1b
this bit is set to 1b. Auto-negotiation automatically
restarts after hardware or software reset
regardless of whether or not the Restart bit (0.9) is
set.
1b = Restart auto-negotiation process.
0b = Normal operation.
Changes to this bit are disruptive to the normal
operation; therefore, any changes to these
registers must be followed by a software reset to
take effect. A write to this register bit does not
take effect until any one of the following also
occurs:
1b = Full-duplex.
0b = Half-duplex.
This bit has no effect.
Changes to this bit are disruptive to the normal
operation; therefore, any changes to these
registers must be followed by a software reset to
take effect. A write to this register bit does not
take effect until any one of the following occurs:
11b = Reserved.
10b = 1000 Mb/s.
01b = 100 Mb/s.
00b = 10 Mb/s.
Reserved, always 0x0.
• Software reset is asserted (register 0.15).
• Restart auto-negotiation is asserted (register
• Power down (register 0.11, 16_0.2) transitions
• Software reset is asserted (register 0.15).
• Restart auto-negotiation is asserted (register
• Power down (register 0.11, 16_0.2) transitions
0.9).
from power down to normal operation.
0.9).
from power down to normal operation (bit 6,
13).
Description