WG82574L S LBA9 Intel, WG82574L S LBA9 Datasheet - Page 87

• Manufacturer Part Number: WG82574L S LBA9
• Description: CONTROLLER, ENET, INTEL 82574L, 64PQFN
• Manufacturer: Intel

Specifications of WG82574L S LBA9

• Ethernet Type: IEEE 802.3, IEEE 802.3u, IEEE 802.3ab
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: 0°C To +85°C
• Digital Ic Case Style: QFN
• No. Of Pins: 64
• Package / Case: QFN
• Interface Type: I2C, JTAG, PCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Power Management and Delivery—82574 GbE Controller
Note:
5.4.3
Table 33.
Note:
5.4.4
5.4.4.1
The AUX Power PM Enable bit in the PCIe Device Control register determines if the
82574 complies with the auxiliary power regime defined in the PCIe specification. If
set, the 82574 might consume higher power for any purpose (such as, even if PME_En
is not set).
If the AUX Power PM Enable bit of the PCIe Device Control register is cleared, higher
power consumption is determined by the PCI-PM legacy PME_En bit in the Power
Management Control / Status Register (PMCSR).
In the current implementation, the AUX Power PM Enable bit is hardwired to 0b.
Power Limits by Certain Form Factors
Table 33
Power Limits by Form Factor
The 82574L therefore implements two NVM bits to disable GbE operation in certain
cases:
The 82574L restarts link auto-negotiation each time it transitions from a state where
GbE speed is enabled to a state where GbE speed is disabled, or vice versa. For
example, if Disable 1000 in non-D0a is set but Disable 1000 is clear, the 82574 restarts
link auto-negotiation on transition from D0 state to D3 or Dr states.
Power States
D0 Uninitialized State
The D0u state is a low-power state used after PE_RST_N is de-asserted following a
power up (cold or warm), on hot reset (in-band reset through a PCIe physical layer
message), or on D3 exit.
Main
Auxiliary (aux enabled)
Auxiliary (aux disabled)
1. This auxiliary current limit only applies when the primary 3.3 V dc voltage source is
2. The 82574L exceeds the allowed power consumption in GbE speed. It therefore
1. The Disable 1000 NVM bit disables 1000 Mb/s operation under all conditions.
2. The Disable 1000 in non-D0a CSR bit disables 1000 Mb/s operation in non-D0a
not available (such as, the NIC is in a low power D3 state.
cannot run from aux power, restricting the 82574 speed in Dr state.
states. If Disable 1000 in non-D0a is set, and the 82574 is at GbE speed on entry
to a non-D0a state, then the device removes advertisement for 1000 Mb/s and
auto-negotiates. The Disable 1000 in non-D0a bit is loaded from the NVM.
lists the power limitations introduced by different form factors.
LOM
3 A @ 3.3 V dc
375 mA @ 3.3 V dc
20 mA @ 3.3 V dc
Form Factor
PCIe NIC (x1 connector)
3 A @ 3.3 V dc
375 mA @ 3.3 V dc
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