WG82574L S LBA9 Intel, WG82574L S LBA9 Datasheet - Page 412

• Manufacturer Part Number: WG82574L S LBA9
• Description: CONTROLLER, ENET, INTEL 82574L, 64PQFN
• Manufacturer: Intel

Specifications of WG82574L S LBA9

• Ethernet Type: IEEE 802.3, IEEE 802.3u, IEEE 802.3ab
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: 0°C To +85°C
• Digital Ic Case Style: QFN
• No. Of Pins: 64
• Package / Case: QFN
• Interface Type: I2C, JTAG, PCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10.2.12
10.2.12.1
Note:
10.2.12.2
412
Diagnostic Register Descriptions
The 82574L contains several diagnostic registers. These registers enable software to
directly access the contents of the 82574’s internal Packet Buffer Memory (PBM), also
referred to as FIFO space. These registers also give software visibility into what
locations in the PBM the hardware currently considers to be the head and tail for both
transmit and receive operations.
PHY OEM Bits Register - POEMB (0x00F10; RW)
The bits in this register are connected to the PHY interface. They affect the auto-
negotiation speed resolution and enable GbE mode. Additionally, PHY class A or B
drivers are also controlled.
1. Bits 7:0 of this register are loaded from NVM word 0x1C[15:8].
When software changes LPLU, D0LPLU or an1000_dis_nd0a it must wait at least 80 ns
and then force the link to auto-negotiate in order to commit the changes to the PHY.
Receive Data FIFO Head Register - RDFH (0x02410; RW)
Reserved
d0lplu
lplu
an1000_dis_n
d0a
class_ab
reautoneg_
now
1000_dis
Auto_update
Pause
Asymmetric
Pause
Reserved
FIFO Head
Reserved
Field
Field
0
1
2
3
4
5
6
7
8
9
31:10
12:0
31:13
Bit(s)
Bit(s)
1b
0b
1b
1b
0b
0b
0b
0b
1b
1b
0x0
0x0
0x0
Initial
Initial
Value
Value
1
1
1
1
1
1
1
1
Reserved
PHY auto negotiation for slowest possible link (reverse auto-
negotiation) in all power states. This bit overrides the LPLU bit.
Enables PHY auto-negotiation for slowest possible link (reverse auto-
negotiation) in all power states except D0a (DR, D0u and D3).
Prevents PHY from auto negotiating 1000 Mb/s link in all power states
except D0a (DR, D0u and D3).
Class AB driver.
This bit can be written by software to force link auto re-negotiation.
Prevents PHY auto-negotiating 1000 Mb/s link in all power states.
Auto-update CB
Disable auto update of the Flash from the shadow RAM when the
ER_RD register is written.
Controls the pause advertisements by the PHY.
1b = MAC pause implemented.
0b = MAC pause not implemented.
Controls the metric pause advertisement by the PHY.
1b = Asymmetric pause supported.
0b = Semantics pause not supported.
Reserved
Receive FIFO Head Pointer
Reads as 0x0. Should be written to 0x0 for future compatibility.
82574 GbE Controller—Driver Programing Interface
Description
Description