WG82574L S LBA9 Intel, WG82574L S LBA9 Datasheet - Page 434

• Manufacturer Part Number: WG82574L S LBA9
• Description: CONTROLLER, ENET, INTEL 82574L, 64PQFN
• Manufacturer: Intel

Specifications of WG82574L S LBA9

• Ethernet Type: IEEE 802.3, IEEE 802.3u, IEEE 802.3ab
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: 0°C To +85°C
• Digital Ic Case Style: QFN
• No. Of Pins: 64
• Package / Case: QFN
• Interface Type: I2C, JTAG, PCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

13.0
13.1
13.1.1
13.1.2
13.1.3
434
Design Considerations
This section provides general design considerations and recommendations when
selecting components and connecting special pins to the 82574.
PCIe
Port Connection to the 82574
PCIe is a dual simplex point-to-point serial differential low-voltage interconnect with a
signaling bit rate of 2.5 Gb/s per direction. The 82574L’s PCIe port consists of an
integral group of transmitters and receivers. The link between the PCIe ports of two
devices is a x1 lane that also consists of a transmitter and a receiver pair. Note that
each signal is 8b/10b encoded with an embedded clock.
The PCIe topology consists of a transmitter (Tx) located on one device connected
through a differential pair connected to the receiver (Rx) on a second device. The
82574L can be located on a motherboard or on an add-in card using a connector
specified by PCIe.
The lane is AC-coupled between its corresponding transmitter and receiver. The AC-
coupling capacitor is located on the board close to transmitter side. Each end of the link
is terminated on the die into nominal 100 differential DC impedance. Board
termination is not required.
For more information on PCIe, refer to the PCI Express* Base Specification, Revision
1.1 and PCI Express* Card Electromechanical Specification, Revision 1.1RD.
For information about the 82574’s PCIe power management capabilities, see
section
PCIe Reference Clock
The 82574L uses a 100 MHz differential reference clock, denoted PECLKp and PECLKn.
This signal is typically generated on the system board and routed to the PCIe port. For
add-in cards, the clock is furnished at the PCIe connector.
The frequency tolerance for the PCIe reference clock is +/- 300 ppm.
Other PCIe Signals
The 82574L also implements other signals required by the PCIe specification. The
82574L signals power management events to the system using the PE_WAKE_N signal,
which operates very similarly to the familiar PCI PME# signal. Finally, there is a
PE_RST_N signal, which serves as the familiar reset function for the 82574.
5.0.
82574 GbE Controller—Design Considerations