WG82574L S LBA9 Intel, WG82574L S LBA9 Datasheet - Page 93

• Manufacturer Part Number: WG82574L S LBA9
• Description: CONTROLLER, ENET, INTEL 82574L, 64PQFN
• Manufacturer: Intel

Specifications of WG82574L S LBA9

• Ethernet Type: IEEE 802.3, IEEE 802.3u, IEEE 802.3ab
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: 0°C To +85°C
• Digital Ic Case Style: QFN
• No. Of Pins: 64
• Package / Case: QFN
• Interface Type: I2C, JTAG, PCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Power Management and Delivery—82574 GbE Controller
Figure 22.
Table 35.
D3cold Transition Timing Diagram
Notes to D3cold Timing Diagram
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Note
Internal PCIe clock
Wake Up Enabled
Reading EEPROM
PHY Power State
Internal PwrGd
PCIe Reference
Reset to PHY
PCIe PwrGd
(active low)
(2.5 GHz)
PCIe Link
Writing 11b to the Power State field of the PMCSR transitions the 82574 to D3. PCIe link transitions
to L1 state.
The system can delay an arbitrary amount of time between setting D3 mode and transition the link to
an L2 or L3 state.
Following link transition, PE_RST_N is asserted.
The system must assert PE_RST_N before stopping the PCIe reference clock. It must also wait tl2clk
after link transition to L2/L3 before stopping the reference clock.
On assertion of PE_RST_N, the 82574 transitions to Dr state.
The system starts the PCIe reference clock t
The Internal PCIe clock is valid and stable t
The PCIe Internal PWRGD signal is asserted tclkpr after the external PE_RST_N signal.
Asserting Internal PCIe PWRGD causes the NVM to be re-read, asserts PHY reset, and disables wake
up.
APM wake-up mode can be enabled based on what is read from the NVM.
After reading the NVM, PHY reset is de-asserted.
Link training starts after tpgtrn from PE_RST_N de-assertion.
A first PCIe configuration access might arrive after t
A first PCI configuration response can be sent after tpgres from PE_RST_N de-assertion
Writing a 1b to the Memory Access Enable bit in the PCI Command register transitions the device
from the D0u to D0 state.
DState
Clock
(PLL)
D0a
D3 write
L0
full
1
L1
D3
Any mode
2
t
t
L0
clkp
l2pg
g
3
4a
t
l2clk
4b
5
power-managed
t
pgdl
L2/L3
t
ppg-clkint
PWRGD-CLK
tppg-
clkint
Description
PWRGD-CLK
Dr
6
7
8
from PE_RST_N de-assertion.
pgcfg
tclkp
9
r
before de-asserting PE_RST_N.
Read
Auto
from PE_RST_N de-assertion.
10
tee
11
Conf.
Ext.
t
pgtrn
12
tpgcfg
13
APM/SMBus
t
pgres
14
L0
D0u
15
full
D0a
93