WG82574L S LBA9 Intel, WG82574L S LBA9 Datasheet - Page 58

• Manufacturer Part Number: WG82574L S LBA9
• Description: CONTROLLER, ENET, INTEL 82574L, 64PQFN
• Manufacturer: Intel

Specifications of WG82574L S LBA9

• Ethernet Type: IEEE 802.3, IEEE 802.3u, IEEE 802.3ab
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: 0°C To +85°C
• Digital Ic Case Style: QFN
• No. Of Pins: 64
• Package / Case: QFN
• Interface Type: I2C, JTAG, PCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Note:
Note:
3.3.7.3
3.3.8
3.3.8.1
3.3.8.2
58
When software accesses the EEPROM or Flash spaces via the bit banging interface, it
should follow these steps:
Following a write or erase instruction, software should clear the Request bit only after it
checked that the cycles were completed by the NVM.
CSR Mapped Firmware Interface
Firmware might access the NVM or shadow RAM via the NVM MNG Control registers in
the CSR space with the following capabilities:
NVM Write and Erase Sequence
When software accesses the EEPROM or Flash CSR registers to the bit banging interface
it should follow these steps:
Software initiates a write cycle to the NVM on the parallel EEPROM as follows:
As a response, hardware executes the following steps:
Case 1 - The 82574L is connected to a physical EEPROM device:
Software Flow to the Bit Banging Interface
Software Byte Program Flow to the EEPROM Interface
1. Write a 1b to the Request bit in the FLA or EEC registers.
2. Poll the Grant bit in the FLA or EEC registers until its ready.
3. Access the NVM using the direct interface to its signaling via the EEC or FLA
4. When access completes, software should clear the Request bit.
1. Write a 1b to the Request bit in the FLA or EEC registers.
2. Poll the Grant bit in the FLA or EEC registers until its ready.
3. Access the NVM using the direct interface to its signaling via the EEC or FLA
4. When access is achieved, software should clear the Request bit. Note that following
1. Poll the Done bit in the EEWR register until its set.
2. Write the data word, its address, and the Start bit to the EEWR register.
1. Initiate an autonomous write enable instruction.
2. Initiate the program instruction right after the enable instruction.
3. Poll the EEPROM status until programming completes.
4. Set the Done bit in the EEWR register.
• Word read and write accesses to the EEPROM or shadow RAM via the EEMNGCTL
• Read and write DMA and block erase to the Flash interface via the FLMNGCTL and
registers.
and EEMNGDATA registers.
FLMNGDATA registers. Flash accesses are mapped to the physical NVM at offset
0x0. Note that nominal accesses to the first two 4 KB sectors should be addressed
to the shadow RAM via the EEPROM interface.
registers.
a write or erase instruction, software should clear the Request bit only after it
checked that the cycles were completed by the NVM.
82574 GbE Controller—Interconnects