WG82574L S LBA9 Intel, WG82574L S LBA9 Datasheet - Page 261

• Manufacturer Part Number: WG82574L S LBA9
• Description: CONTROLLER, ENET, INTEL 82574L, 64PQFN
• Manufacturer: Intel

Specifications of WG82574L S LBA9

• Ethernet Type: IEEE 802.3, IEEE 802.3u, IEEE 802.3ab
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: 0°C To +85°C
• Digital Ic Case Style: QFN
• No. Of Pins: 64
• Package / Case: QFN
• Interface Type: I2C, JTAG, PCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Programing Interface—82574 GbE Controller
9.1.2.4
9.1.2.5
9.1.2.6
9.1.2.7
9.1.2.8
9.1.2.9
Status Register (Offset 0x6)
Shaded fields are not used by this implementation and are hardwired to 0b.
1. The Interrupt Status field is a read-only field that indicates that an interrupt message is
Revision ID (Offset 0x8)
The default revision ID of this device is 0x0. The value of the rev ID is a logic XOR
between the default value and the value in the NVM word 0x1E.
Class Code (Offset 0x9)
The class code is a read-only, hard-coded value that identifies the device functionality.
LAN - 0x020000 - Ethernet Adapter
Cache Line Size (Offset 0xC)
This field is implemented by PCIe devices as a read-write field for legacy compatibility
purposes but has no impact on any PCIe device functionality. Loaded from NVM words
0x1A.
Latency Timer (Offset 0xD)
Not used. Hardwired to 0b.
Header Type (Offset 0xE)
This indicates if a device is single function or multifunction. For the 82574 this field has
a value of 0x00 to indicate a single function device.
2:0
3
4
5
6
7
8
10:9
11
12
13
14
15
Bits
pending internally to the device.
000b
0b
1b
0b
0b
0b
0b
00b
0
0bb
0b
0b
0b
Initial
Value
RO
RO
R/W1C
R/W1C
R/W1C
R/W1C
R/W1C
R/W1C
R/W
Reserved
Interrupt Status
New Capabilities
Indicates that a device implements extended capabilities. The
82574L sets this bit, and implements a capabilities list, to
indicate that it supports PCI power management, message
signaled interrupts, and the PCIe extensions.
66MHz Capable – Hardwired to 0b.
Reserved.
Fast Back-to-Back Capable – Hardwired to 0b.
Data Parity Reported.
DEVSEL Timing – Hardwired to 0b.
Signaled Target Abort.
Received Target Abort.
Received Master Abort.
Signaled System Error.
Detected Parity Error.
1
Description
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