AT90USB647-MU Atmel, AT90USB647-MU Datasheet - Page 246

• Manufacturer Part Number: AT90USB647-MU
• Description: MCU, 8BIT, 64K FLASH, USB, 64QFN
• Manufacturer: Atmel

Specifications of AT90USB647-MU

• Controller Family/series: AT90
• No. Of I/o's: 48
• Eeprom Memory Size: 2KB
• Ram Memory Size: 4KB
• Cpu Speed: 16MHz
• No. Of: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 64KB
• Oscillator Type: External, Internal
• Package: 64QFN EP
• Device Core: AVR
• Family Name: AT90
• Maximum Speed: 20 MHz
• Ram Size: 4 KB
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 8 Bit
• Program Memory Type: Flash
• Number Of Programmable I/os: 48
• Interface Type: SPI/TWI/USART/USB
• On-chip Adc: 8-chx10-bit
• Operating Temperature: -40 to 85 °C
• Number Of Timers: 4
• Lead Free Status / Rohs Status: Details

21. USB controller
21.1
21.2
246
Features
Block Diagram
AT90USB64/128
•
•
•
The USB controller provides the hardware to interface a USB link to a data flow stored in a dou-
ble port memory (DPRAM).
The USB controller requires a 48 MHz ±0.25% reference clock (for Full-Speed operation), which
is the output of an internal PLL. The PLL generates the internal high frequency (48 MHz) clock
for USB interface, the PLL input is generated from an external lower frequency (the crystal oscil-
lator or external clock input pin from XTAL1; to satisfy the USB frequency accuracy and jitter,
only this clock source allows proper functionnality of the USB controller).
The 48MHz clock is used to generate a 12 MHz Full-speed (or 1.5 MHz Low-Speed) bit clock
from the received USB differential data and to transmit data according to full or low speed USB
device tolerance. Clock recovery is done by a Digital Phase Locked Loop (DPLL) block, which is
compliant with the jitter specification of the USB bus.
To comply with the USB Electrical specification, USB Pads (D+ or D-) should be powered within
the 3.0 to 3.6V range. As AT90USB64/128 can be powered up to 5.5V, an internal regulator pro-
vides the USB pads power supply.
Figure 21-1. USB controller Block Diagram overview
Support full-speed and low-speed.
Support ping-pong mode (dual bank)
832 bytes of DPRAM :
– 1 endpoint 64 bytes max (default control endpoint),
– 1 endpoints of 256 bytes max, (one or two banks),
– 5 endpoints of 64 bytes max, (one or two banks)
UCAP
VBUS
D-
D+
UID
USB Regulator
Recovery
DPLL
Clock
UVCC
Interface
USB
clk
48MHz
AVCC
PLL
24x
clk
2MHz
USB DPRAM
PLL clock
Prescaler
On-Chip
CPU
XTAL1
7593K–AVR–11/09