AT90USB647-MU Atmel, AT90USB647-MU Datasheet - Page 381

• Manufacturer Part Number: AT90USB647-MU
• Description: MCU, 8BIT, 64K FLASH, USB, 64QFN
• Manufacturer: Atmel

Specifications of AT90USB647-MU

• Controller Family/series: AT90
• No. Of I/o's: 48
• Eeprom Memory Size: 2KB
• Ram Memory Size: 4KB
• Cpu Speed: 16MHz
• No. Of: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 64KB
• Oscillator Type: External, Internal
• Package: 64QFN EP
• Device Core: AVR
• Family Name: AT90
• Maximum Speed: 20 MHz
• Ram Size: 4 KB
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 8 Bit
• Program Memory Type: Flash
• Number Of Programmable I/os: 48
• Interface Type: SPI/TWI/USART/USB
• On-chip Adc: 8-chx10-bit
• Operating Temperature: -40 to 85 °C
• Number Of Timers: 4
• Lead Free Status / Rohs Status: Details

29.8
29.8.1
7593K–AVR–11/09
Serial Programming Pin Mapping
Serial Programming Algorithm
Table 29-14. Pin Mapping Serial Programming
Figure 29-10. Serial Programming and Verify
Notes:
When programming the EEPROM, an auto-erase cycle is built into the self-timed programming
operation (in the Serial mode ONLY) and there is no need to first execute the Chip Erase
instruction. The Chip Erase operation turns the content of every memory location in both the
Program and EEPROM arrays into 0xFF.
Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high periods
for the serial clock (SCK) input are defined as follows:
Low: > 2 CPU clock cycles for f
High: > 2 CPU clock cycles for f
When writing serial data to the AT90USB64/128, data is clocked on the rising edge of SCK.
When reading data from the AT90USB64/128, data is clocked on the falling edge of SCK. See
Figure 29-11
To program and verify the AT90USB64/128 in the serial programming mode, the following
sequence is recommended (See four byte instruction formats in
Symbol
PDO
SCK
PDI
1. If the device is clocked by the internal Oscillator, it is no need to connect a clock source to the
2. V
XTAL1 pin.
CC
for timing details.
- 0.3V < AVCC < V
(TQFP-64)
Pins
PB2
PB3
PB1
PDO
SCK
PDI
ck
ck
CC
< 12 MHz, 3 CPU clock cycles for f
< 12 MHz, 3 CPU clock cycles for f
+ 0.3V, however, AVCC should always be within 1.8 - 5.5V
XTAL1
RESET
GND
I/O
O
I
I
(1)
AVCC
VCC
Serial Data out
Serial Data in
Description
Serial Clock
+1.8 - 5.5V
+1.8 - 5.5V
Table
AT90USB64/128
(2)
ck
ck
29-16):
>= 12 MHz
>= 12 MHz
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