AT90USB647-MU Atmel, AT90USB647-MU Datasheet - Page 330

• Manufacturer Part Number: AT90USB647-MU
• Description: MCU, 8BIT, 64K FLASH, USB, 64QFN
• Manufacturer: Atmel

Specifications of AT90USB647-MU

• Controller Family/series: AT90
• No. Of I/o's: 48
• Eeprom Memory Size: 2KB
• Ram Memory Size: 4KB
• Cpu Speed: 16MHz
• No. Of: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 64KB
• Oscillator Type: External, Internal
• Package: 64QFN EP
• Device Core: AVR
• Family Name: AT90
• Maximum Speed: 20 MHz
• Ram Size: 4 KB
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 8 Bit
• Program Memory Type: Flash
• Number Of Programmable I/os: 48
• Interface Type: SPI/TWI/USART/USB
• On-chip Adc: 8-chx10-bit
• Operating Temperature: -40 to 85 °C
• Number Of Timers: 4
• Lead Free Status / Rohs Status: Details

25.8.3.2
25.8.4
330
AT90USB64/128
ADC Control and Status Register B – ADCSRB
ADLAR = 1
When an ADC conversion is complete, the result is found in these two registers. If differential
channels are used, the result is presented in two’s complement form.
When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if
the result is left adjusted and no more than 8-bit precision (7 bit + sign bit for differential input
channels) is required, it is sufficient to read ADCH. Otherwise, ADCL must be read first, then
ADCH.
The ADLAR bit in ADMUX, and the MUXn bits in ADMUX affect the way the result is read from
the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result
is right adjusted.
• ADC9:0: ADC Conversion Result
These bits represent the result from the conversion, as detailed in
page
• Bit 7 – ADHSM: ADC High Speed Mode
Writing this bit to one enables the ADC High Speed mode. This mode enables higher conversion
rate at the expense of higher power consumption.
• Bit 2:0 – ADTS2:0: ADC Auto Trigger Source
If ADATE in ADCSRA is written to one, the value of these bits selects which source will trigger
an ADC conversion. If ADATE is cleared, the ADTS2:0 settings will have no effect. A conversion
will be triggered by the rising edge of the selected interrupt flag. Note that switching from a trig-
ger source that is cleared to a trigger source that is set, will generate a positive edge on the
trigger signal. If ADEN in ADCSRA is set, this will start a conversion. Switching to Free Running
mode (ADTS[2:0]=0) will not cause a trigger event, even if the ADC Interrupt Flag is set
Table 25-6.
Bit
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
ADTS2
324.
0
0
0
0
ADHSM
ADC9
ADC1
ADC Auto Trigger Source Selections
R/W
15
R
R
7
0
0
7
0
ADC8
ADC0
ADTS1
ACME
R/W
14
R
R
6
0
0
6
0
0
0
1
1
ADC7
13
R
R
–
5
0
0
R
5
–
0
ADC6
ADTS0
12
R
R
–
4
0
0
R
4
–
0
0
1
0
1
ADC5
11
R
R
–
3
0
0
R
3
–
0
Trigger Source
Free Running mode
Analog Comparator
External Interrupt Request 0
Timer/Counter0 Compare Match
ADTS2
ADC4
R/W
10
R
R
–
2
0
0
2
0
ADTS1
ADC3
R/W
R
R
9
–
1
0
0
1
0
“ADC Conversion Result” on
ADTS0
ADC2
R/W
R
R
8
–
0
0
0
0
0
ADCSRB
ADCH
ADCL
7593K–AVR–11/09
.