AT90USB647-MU Atmel, AT90USB647-MU Datasheet - Page 82

• Manufacturer Part Number: AT90USB647-MU
• Description: MCU, 8BIT, 64K FLASH, USB, 64QFN
• Manufacturer: Atmel

Specifications of AT90USB647-MU

• Controller Family/series: AT90
• No. Of I/o's: 48
• Eeprom Memory Size: 2KB
• Ram Memory Size: 4KB
• Cpu Speed: 16MHz
• No. Of: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 64KB
• Oscillator Type: External, Internal
• Package: 64QFN EP
• Device Core: AVR
• Family Name: AT90
• Maximum Speed: 20 MHz
• Ram Size: 4 KB
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 8 Bit
• Program Memory Type: Flash
• Number Of Programmable I/os: 48
• Interface Type: SPI/TWI/USART/USB
• On-chip Adc: 8-chx10-bit
• Operating Temperature: -40 to 85 °C
• Number Of Timers: 4
• Lead Free Status / Rohs Status: Details

82
AT90USB64/128
PCINT1, Pin Change Interrupt source 1: The PB1 pin can serve as an external interrupt source.
• SS/PCINT0 – Port B, Bit 0
SS: Slave Port Select input. When the SPI is enabled as a slave, this pin is configured as an
input regardless of the setting of DDB0. As a slave, the SPI is activated when this pin is driven
low. When the SPI is enabled as a master, the data direction of this pin is controlled by DDB0.
When the pin is forced to be an input, the pull-up can still be controlled by the PORTB0 bit.
Table 10-7
shown in
MISO signal, while MOSI is divided into SPI MSTR OUTPUT and SPI SLAVE INPUT.
PCINT0, Pin Change Interrupt source 0: The PB0 pin can serve as an external interrupt source..
Table 10-7.
Table 10-8.
Signal
Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
DIEOE
DIEOV
DI
AIO
Signal
Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
DIEOE
DIEOV
DI
AIO
Figure 10-5 on page
PB7/PCINT7/OC0A/
OC1C
0
0
0
0
OC0/OC1C ENABLE
OC0/OC1C
PCINT7 • PCIE0
1
PCINT7 INPUT
–
PB3/PD0/PCINT3/
MISO
SPE • MSTR
PORTB3 • PUD
SPE • MSTR
0
SPE • MSTR
SPI SLAVE OUTPUT
PCINT3 • PCIE0
1
SPI MSTR INPUT
PCINT3 INPUT
–
and
Overriding Signals for Alternate Functions in PB7..PB4
Overriding Signals for Alternate Functions in PB3..PB0
Table 10-8
relate the alternate functions of Port B to the overriding signals
77. SPI MSTR INPUT and SPI SLAVE OUTPUT constitute the
PB2/PDI/PCINT2/
MOSI
SPE • MSTR
PORTB2 • PUD
SPE • MSTR
0
SPE • MSTR
SPI MSTR OUTPUT
PCINT2 • PCIE0
1
SPI SLAVE INPUT
PCINT2 INPUT
–
PB6/PCINT6/OC
1B
0
0
0
0
OC1B ENABLE
OC1B
PCINT6 • PCIE0
1
PCINT6 INPUT
–
PB5/PCINT5/OC
1A
0
0
0
0
OC1A ENABLE
OC1A
PCINT5 • PCIE0
1
PCINT5 INPUT
–
PB1/PCINT1/
SCK
SPE • MSTR
PORTB1 • PUD
SPE • MSTR
0
SPE • MSTR
SCK OUTPUT
PCINT1 •
PCIE0
1
SCK INPUT
PCINT1 INPUT
–
PB4/PCINT4/OC
2A
0
0
0
0
OC2A ENABLE
OC2A
PCINT4 • PCIE0
1
PCINT4 INPUT
–
PB0/PCINT0/
SS
SPE • MSTR
PORTB0 • PUD
SPE • MSTR
0
0
0
PCINT0 •
PCIE0
1
SPI SS
PCINT0 INPUT
–
7593K–AVR–11/09