AT90USB647-MU Atmel, AT90USB647-MU Datasheet - Page 291

• Manufacturer Part Number: AT90USB647-MU
• Description: MCU, 8BIT, 64K FLASH, USB, 64QFN
• Manufacturer: Atmel

Specifications of AT90USB647-MU

• Controller Family/series: AT90
• No. Of I/o's: 48
• Eeprom Memory Size: 2KB
• Ram Memory Size: 4KB
• Cpu Speed: 16MHz
• No. Of: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 64KB
• Oscillator Type: External, Internal
• Package: 64QFN EP
• Device Core: AVR
• Family Name: AT90
• Maximum Speed: 20 MHz
• Ram Size: 4 KB
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 8 Bit
• Program Memory Type: Flash
• Number Of Programmable I/os: 48
• Interface Type: SPI/TWI/USART/USB
• On-chip Adc: 8-chx10-bit
• Operating Temperature: -40 to 85 °C
• Number Of Timers: 4
• Lead Free Status / Rohs Status: Details

23.4
23.5
23.6
7593K–AVR–11/09
Device Detection
Pipe Selection
Pipe Configuration
USB host controller state after an hardware reset is ‘Reset’. When the USB controller is enabled
and the USB Host controller is selected, the USB controller is in ‘Idle’ state. In this state, the
USB Host controller waits for the Device connection, with a minimum power consumption.
The USB Pad should be in Idle mode. The macro does not need to have the PLL activated to
enter in ‘Host Ready’ state.
The Host controller enters in Suspend state when the USB bus is in Suspend state, i.e. when the
Host controller doesn’t generate the Start of Frame. In this state, the USB consumption is mini-
mum. The Host controller exits to the Suspend state when starting to generate the SOF over the
USB line.
A Device is detected by the USB controller when the USB bus if different from D+ and D- low. In
other words, when the USB Host Controller detects the Device pull-up on the D+ line. To enable
this detection, the Host Controller has to provide the Vbus power supply to the Device.
The Device Disconnection is detected by the USB Host controller when the USB Idle correspond
to D+ and D- low on the USB line.
Prior to any operation performed by the CPU, the Pipe must first be selected. This is done by
setting PNUM2:0 bits (UPNUM register) with the Pipe number which will be managed by the
CPU.
The CPU can then access to the various Pipe registers and data.
The following flow must be respected in order to activate a Pipe:
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