UPD78F0413GA-GAM-AX NEC, UPD78F0413GA-GAM-AX Datasheet - Page 134
![8BIT UC, 32K FLASH, 1KB RAM, LCD](/photos/19/0/190032/ge48lqfp05-40_sml.jpg)
UPD78F0413GA-GAM-AX
Manufacturer Part Number
UPD78F0413GA-GAM-AX
Description
8BIT UC, 32K FLASH, 1KB RAM, LCD
Manufacturer
NEC
Datasheet
1.UPD78F0413GA-GAM-AX.pdf
(562 pages)
Specifications of UPD78F0413GA-GAM-AX
Controller Family/series
UPD78F
No. Of I/o's
30
Ram Memory Size
1024Byte
Cpu Speed
10MHz
No. Of Timers
8
No. Of Pwm
RoHS Compliant
Core Size
8bit
Program Memory Size
32KB
Oscillator Type
External, Internal
Available stocks
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Part Number:
UPD78F0413GA-GAM-AX
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ADI
Quantity:
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Part Number:
UPD78F0413GA-GAM-AX
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5.6.6 CPU clock status transition diagram
134
Internal low-speed oscillation: Operable
Internal high-speed oscillation:
Selectable by CPU
X1 oscillation/EXCLK input:
Selectable by CPU
XT1 oscillation input: Operating
Figure 5-15 shows the CPU clock status transition diagram of this product.
Remark In the 2.7 V/1.59 V POC mode (option byte: POCMODE = 1), the CPU clock status changes to (A) in the
Internal low-speed oscillation: Operable
Internal high-speed oscillation: Operable
X1 oscillation/EXCLK input: Operable
XT1 oscillation input: Operating
above figure when the supply voltage exceeds 2.7 V (TYP.), and to (B) after reset processing (11 to 47
s (TYP.)).
(D)
(When 1.59 V POC Mode Is Set (Option Byte: POCMODE = 0))
(G)
with XT1 oscillation
Internal low-speed oscillation: Operable
Internal high-speed oscillation: Operating
X1 oscillation/EXCLK input:
Selectable by CPU
XT1 oscillation input: Selectable by CPU
oscillation input
CPU: Operating
CPU: XT1
Figure 5-15. CPU Clock Status Transition Diagram
input
HALT
Internal low-speed oscillation: Operable
Internal high-speed oscillation:
Selectable by CPU
X1 oscillation/EXCLK input: Operating
XT1 oscillation input: Selectable by CPU
CHAPTER 5 CLOCK GENERATOR
User’s Manual U18698EJ1V0UD
(A)
(B)
(C)
with X1 oscillation or
Reset release
with internal high-
speed oscillation
CPU: Operating
CPU: Operating
Power ON
EXCLK input
(F)
oscillation/EXCLK
input
CPU: X1
HALT
Internal low-speed oscillation:
Operable
Internal high-speed oscillation:
Operable
X1 oscillation/EXCLK input: Operating
XT1 oscillation input: Operable
Internal low-speed oscillation: Woken up
Internal high-speed oscillation: Woken up
X1 oscillation/EXCLK input: Stops (I/O port mode)
XT1 oscillation input: Stops (Input port mode)
Internal low-speed oscillation: Operating
Internal high-speed oscillation: Operating
X1 oscillation/EXCLK input: Stops (I/O port mode)
XT1 oscillation input: Stops (Input port mode)
(H)
(E)
(I)
CPU: Internal high-
oscillation/EXCLK
CPU: Internal high-
speed oscillation
speed oscillation
input
V
V
V
CPU: X1
DD
DD
DD
STOP
HALT
< 1.59 V (TYP.)
1.59 V (TYP.)
1.8 V (MIN.)
STOP
Internal low-speed oscillation:
Operable
Internal high-speed oscillation:
Stops
X1 oscillation/EXCLK input: Stops
XT1 oscillation: Operable
Internal low-speed oscillation:
Operable
Internal high-speed oscillation:
Stops
X1 oscillation/EXCLK input: Stops
XT1 oscillation input: Operable
Internal low-speed oscillation:
Operable
Internal high-speed oscillation:
Operating
X1 oscillation/EXCLK input: Operable
XT1 oscillation input: Operable
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