UPD78F0413GA-GAM-AX NEC, UPD78F0413GA-GAM-AX Datasheet - Page 138

• Manufacturer Part Number: UPD78F0413GA-GAM-AX
• Description: 8BIT UC, 32K FLASH, 1KB RAM, LCD
• Manufacturer: NEC

Specifications of UPD78F0413GA-GAM-AX

• Controller Family/series: UPD78F
• No. Of I/o's: 30
• Ram Memory Size: 1024Byte
• Cpu Speed: 10MHz
• No. Of Timers: 8
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 32KB
• Oscillator Type: External, Internal

(9) CPU clock changing from subsystem clock (D) to high-speed system clock (C)
Note The value of this flag can be changed only once after a reset release. This setting is not necessary if it has
Caution Set the clock after the supply voltage has reached the operable voltage of the clock to be set (see
(10) HALT mode (E) set while CPU is operating with internal high-speed oscillation clock (B)
(11) STOP mode (H) set while CPU is operating with internal high-speed oscillation clock (B)
138
(B)
(C)
(D)
Status Transition
(D)
(D)
(B)
(C)
Remarks 1. (A) to (I) in Table 5-5 correspond to (A) to (I) in Figure 5-15.
already been set.
HALT mode (F) set while CPU is operating with high-speed system clock (C)
HALT mode (G) set while CPU is operating with subsystem clock (D)
STOP mode (I) set while CPU is operating with high-speed system clock (C)
(E)
(F)
(G)
(H)
(C) (X1 clock)
(C) (external main clock)
(I)
(Setting sequence of SFR registers)
CHAPTER 27 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS)).
2. EXCLK, OSCSEL:
Setting Flag of SFR Register
Status Transition
Status Transition
MSTOP:
XSEL, MCM0:
CSS:
Table 5-5. CPU Clock Transition and SFR Register Setting Examples (4/4)
(Setting sequence)
CHAPTER 5 CLOCK GENERATOR
Unnecessary if these
registers are already
EXCLK
Bits 7 and 6 of the clock operation mode select register (OSCCTL)
Bit 7 of the main OSC control register (MOC)
Bits 2 and 0 of the main clock mode register (MCM)
Bit 4 of the processor clock control register (PCC)
0
1
User’s Manual U18698EJ1V0UD
Executing HALT instruction
Stopping peripheral functions that
cannot operate in STOP mode
set
OSCSEL
1
1
the high-speed system
CPU is operating with
MSTOP
Unnecessary if the
0
0
clock
Must not be
checked
Must be
Register
checked
OSTC
Setting
Setting
Executing STOP instruction
XSEL
1
1
Note
MCM0
1
1
CSS
0
0