UPD78F0413GA-GAM-AX NEC, UPD78F0413GA-GAM-AX Datasheet - Page 147

• Manufacturer Part Number: UPD78F0413GA-GAM-AX
• Description: 8BIT UC, 32K FLASH, 1KB RAM, LCD
• Manufacturer: NEC

Specifications of UPD78F0413GA-GAM-AX

• Controller Family/series: UPD78F
• No. Of I/o's: 30
• Ram Memory Size: 1024Byte
• Cpu Speed: 10MHz
• No. Of Timers: 8
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 32KB
• Oscillator Type: External, Internal

Operation as interval timer
Operation as square-wave output
Operation as external event counter
Operation in the clear & start mode
entered by TI000 pin valid edge input
Operation as free-running timer
Operation as PPG output
Operation as one-shot pulse output
Note When 0000H is set, a match interrupt immediately after the timer operation does not occur and timer output
Remarks 1. N: CR000 register set value, M: CR010 register set value
(iii) Setting range when CR000 or CR010 is used as a compare register
When CR000 or CR010 is used as a compare register, set it as shown below.
is not changed, and the first match timing is as follows. A match interrupt occurs at the timing when the
timer counter (TM00 register) is changed from 0000H to 0001H.
When the timer counter is cleared due to overflow
When the timer counter is cleared due to TI000 pin valid edge (when clear & start mode is entered by
TI000 pin valid edge input)
When the timer counter is cleared due to compare match (when clear & start mode is entered by match
between TM00 and CR000 (CR000 = other than 0000H, CR010 = 0000H))
2. For details of TMC003 and TMC002, see 6.3 (1) 16-bit timer mode control register 00 (TMC00).
Operation
Compare register set value
Timer operation enable bit
Interrupt request signal
(TMC003, TMC002)
CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00
TM00 register
(0000H)
0000H < N
0000H
M < N
0000H
CR000 Register Setting Range
User’s Manual U18698EJ1V0UD
Note
Note
FFFFH
disabled (00)
Operation
N
N
FFFFH
is not generated
Interrupt signal
FFFFH
FFFFH (N
Timer counter clear
Operation enabled
(other than 00)
M)
0000H
Normally, this setting is not used. Mask the
match interrupt signal (INTTM010).
0000H
0000H
0000H
Interrupt signal
is generated
Note
Note
Note
Note
CR010 Register Setting Range
M
M
M < N
M
FFFFH
FFFFH
FFFFH (M
N)
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