UPD78F0413GA-GAM-AX NEC, UPD78F0413GA-GAM-AX Datasheet - Page 97

• Manufacturer Part Number: UPD78F0413GA-GAM-AX
• Description: 8BIT UC, 32K FLASH, 1KB RAM, LCD
• Manufacturer: NEC

Specifications of UPD78F0413GA-GAM-AX

• Controller Family/series: UPD78F
• No. Of I/o's: 30
• Ram Memory Size: 1024Byte
• Cpu Speed: 10MHz
• No. Of Timers: 8
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 32KB
• Oscillator Type: External, Internal

(2) Port registers (P1 to P4, P10 to P12, P14, P15)
Symbol
P11
P10
P12
P14
P15
P1
P2
P3
P4
These registers write the data that is output from the chip when data is output from a port.
If the data is read in the input mode, the pin level is read. If it is read in the output mode, the output latch value is
read.
These registers can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears these registers to 00H.
Notes 1.
Pmn
0
0
0
7
0
0
0
0
0
0
0
1
2.
Output 0
Output 1
P121 to P124 are read-only. These become undefined at reset.
When the operation mode of the pin is the clock input mode, 0 is always read.
0
0
6
0
0
0
0
0
0
0
Output data control (in output mode)
P25
5
0
0
0
0
0
0
0
0
P124
P24
P34
4
0
0
0
0
0
0
Figure 4-17 Format of Port Register
Note 2
CHAPTER 4 PORT FUNCTIONS
P123
User’s Manual U18698EJ1V0UD
P113
P143
P153
P13
P23
P33
3
0
0
Note 2
m = 1 to 4, 10 to 12, 14, 15; n = 0 to 5
P122
P112
P142
P152
P12
P22
P32
2
0
0
Note 2
P121
P101
P141
P151
P21
P31
1
0
0
0
Note 2
Input low level
Input high level
P100
P140
P150
P120
P20
P40
0
0
0
0
Input data read (in input mode)
Address
FF0BH
FF0CH
FF01H
FF02H
FF03H
FF04H
FF0AH
FF0EH
FF0FH
00H
00H (output latch)
00H (output latch)
00H (output latch)
00H (output latch)
00H (output latch)
00H (output latch)
00H (output latch)
00H (output latch)
Note 1
After reset
(output latch) R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Note 1
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