UPD78F0413GA-GAM-AX NEC, UPD78F0413GA-GAM-AX Datasheet - Page 341

• Manufacturer Part Number: UPD78F0413GA-GAM-AX
• Description: 8BIT UC, 32K FLASH, 1KB RAM, LCD
• Manufacturer: NEC

Specifications of UPD78F0413GA-GAM-AX

• Controller Family/series: UPD78F
• No. Of I/o's: 30
• Ram Memory Size: 1024Byte
• Cpu Speed: 10MHz
• No. Of Timers: 8
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 32KB
• Oscillator Type: External, Internal

(1) Receive buffer register 6 (RXB6)
(2) Receive shift register 6 (RXS6)
(3) Transmit buffer register 6 (TXB6)
(4) Transmit shift register 6 (TXS6)
This 8-bit register stores parallel data converted by receive shift register 6 (RXS6).
Each time 1 byte of data has been received, new receive data is transferred to this register from RXS6. If the
data length is set to 7 bits, data is transferred as follows.
If an overrun error (OVE6) occurs, the receive data is not transferred to RXB6.
RXB6 can be read by an 8-bit memory manipulation instruction. No data can be written to this register.
Reset signal generation sets this register to FFH.
This register converts the serial data input to the R
RXS6 cannot be directly manipulated by a program.
This buffer register is used to set transmit data. Transmission is started when data is written to TXB6.
This register can be read or written by an 8-bit memory manipulation instruction.
Reset signal generation sets this register to FFH.
Cautions 1. Do not write data to TXB6 when bit 1 (TXBF6) of asynchronous serial interface transmission
This register transmits the data transferred from TXB6 from the T
TXB6 immediately after TXB6 is written for the first transmission, or immediately before INTST6 occurs after one
frame was transmitted for continuous transmission. Data is transferred from TXB6 and transmitted from the T
pin at the falling edge of the base clock.
TXS6 cannot be directly manipulated by a program.
In LSB-first reception, the receive data is transferred to bits 0 to 6 of RXB6 and the MSB of RXB6 is always 0.
In MSB-first reception, the receive data is transferred to bits 1 to 7 of RXB6 and the LSB of RXB6 is always 0.
2. Do not refresh (write the same value to) TXB6 by software during a communication
3. Set transmit data to TXB6 at least one base clock (f
status register 6 (ASIF6) is 1.
operation (when bits 7 and 6 (POWER6, TXE6) of asynchronous serial interface operation
mode register 6 (ASIM6) are 1 or when bits 7 and 5 (POWER6, RXE6) of ASIM6 are 1).
CHAPTER 14 SERIAL INTERFACE UART6
User’s Manual U18698EJ1V0UD
X
D6 pin into parallel data.
X
D6 pin as serial data. Data is transferred from
XCLK6
) after setting TXE6 = 1.
341
X
D6