UPD78F0413GA-GAM-AX NEC, UPD78F0413GA-GAM-AX Datasheet - Page 145

• Manufacturer Part Number: UPD78F0413GA-GAM-AX
• Description: 8BIT UC, 32K FLASH, 1KB RAM, LCD
• Manufacturer: NEC

Specifications of UPD78F0413GA-GAM-AX

• Controller Family/series: UPD78F
• No. Of I/o's: 30
• Ram Memory Size: 1024Byte
• Cpu Speed: 10MHz
• No. Of Timers: 8
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 32KB
• Oscillator Type: External, Internal

(1) 16-bit timer counter 00 (TM00)
(2) 16-bit timer capture/compare register 000 (CR000), 16-bit timer capture/compare register 010 (CR010)
Cautions 2. If clearing of bits 3 and 2 (TMC003 and TMC002) of 16-bit timer mode control register 00
TM00 is a 16-bit read-only register that counts count pulses.
The counter is incremented in synchronization with the rising edge of the count clock.
If the count value is read during operation, then input of the count clock is temporarily stopped, and the count
value at that point is read.
The count value of TM00 can be read by reading TM00 when the value of bits 3 and 2 (TMC003 and TMC002) of
16-bit timer mode control register 00 (TMC00) is other than 00. The value of TM00 is 0000H if it is read when
TMC003 and TMC002 = 00.
The count value is reset to 0000H in the following cases.
Caution
CR000 and CR010 are 16-bit registers that are used with a capture function or comparison function selected by
using CRC00.
Change the value of CR000 while the timer is stopped (TMC003 and TMC002 = 00).
The value of CR010 can be changed during operation if the value has been set in a specific way. For details, see
6.5.1 Rewriting CR010 during TM00 operation.
These registers can be read or written in 16-bit units.
Reset signal generation sets these registers to 0000H.
At reset signal generation
If TMC003 and TMC002 are cleared to 00
If the valid edge of the TI000 pin is input in the mode in which the clear & start occurs when inputting the valid
edge to the TI000 pin
If TM00 and CR000 match in the mode in which the clear & start occurs when TM00 and CR000 match
OSPT00 is set to 1 in one-shot pulse output mode or the valid edge is input to the TI000 pin
Address: FF10H, FF11H
TM00
3. To change the mode from the capture mode to the comparison mode, first clear the TMC003
Even if TM00 is read, the value is not captured by CR010.
(TMC00) to 00 and input of the capture trigger conflict, then the captured data is undefined.
and TMC002 bits to 00, and then change the setting.
A value that has been once captured remains stored in CR000 unless the device is reset. If
the mode has been changed to the comparison mode, be sure to set a comparison value.
15
14
Figure 6-2. Format of 16-Bit Timer Counter 00 (TM00)
13
CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00
After reset: 0000H
12
FF11H
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User’s Manual U18698EJ1V0UD
10
9
R
8
7
6
5
FF10H
4
3
2
1
0
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