IPSR-VIDEO Altera, IPSR-VIDEO Datasheet - Page 130

• Manufacturer Part Number: IPSR-VIDEO
• Description: RENEWAL Of IPS-VIDEO
• Manufacturer: Altera
• Series: IP Suitesr

Specifications of IPSR-VIDEO

• Software Application: IP CORE, SUITES
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Features: Common Avalon Streaming (Avalon-St) Interface And Avalon-St Video Protocol
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

5–50
Video and Image Processing Suite User Guide
1
Video frames are stored in external memory as raw video data (pixel values only).
Immediately before the Frame Reader MegaCore function reads video data from
external memory it generates a control packet and the header of a video data packet
on its Avalon-ST source. The video data from external memory is then streamed as the
payload of the video data packet. The content of the control data packet is set via the
Avalon Slave port. This process is repeated for every video frame read from external
memory.
The Frame Reader is configured during compilation to output a fixed number of color
planes in parallel, and a fixed number of bits per pixel per color plane. In terms of
Avalon-ST Video, these parameters describe the structure of one cycle of a color
pattern, also known as the single-cycle color pattern.
The Frame Reader is also configured with the number of channels in sequence, this
parameter does not contribute to the definition of the single-cycle color pattern.
To configure the Frame Reader to read a frame from memory, the Frame Reader must
know how many single-cycle color patterns make up the frame. If each single-cycle
color pattern represents a pixel, then the quantity is simply the number of pixels in the
frame. Otherwise, the quantity is the number of pixels in the frame, multiplied by the
number of single-cycle color patterns required to represent a pixel.
You must also specify the number of words the Frame Reader must read from
memory. The width of the word is the same as the Avalon-MM read Master port
width parameter. This width is configured during compilation. Each word can only
contain whole single-cycle color patterns. The words cannot contain partial single-
cycle color patterns. Any bits of the word that cannot fit another whole single-cycle
color pattern are not used.
Also, the Frame Reader must be configured with the starting address of the video
frame in memory, and the width, height, and interlaced values of the control data
packet to output before each video data packet.
The raw data that comprises a video frame in external memory is stored as a set of
single-cycle color patterns. In memory, the single-cycle color patterns must be
organized into word-sized sections. Each of these word-sized sections must contain as
many whole samples as possible, with no partial single-cycle color patterns. Unused
bits are in the most significant portion of the word-sized sections. Single-cycle color
patterns in the least significant bits are output first. The frame is read with words at
the starting address first.
Figure 5–25
MegaCore, which is configured for:
■
■
■
8 bits per pixel per color plane
3 color planes in parallel
Master port width 64
shows the output pattern and memory organization for a Frame Reader
Chapter 5: Functional Descriptions
January 2011 Altera Corporation
Frame Reader