IPSR-VIDEO Altera, IPSR-VIDEO Datasheet - Page 40
IPSR-VIDEO
Manufacturer Part Number
IPSR-VIDEO
Description
RENEWAL Of IPS-VIDEO
Manufacturer
Altera
Series
IP Suitesr
Datasheet
1.IPS-VIDEO.pdf
(202 pages)
Specifications of IPSR-VIDEO
Software Application
IP CORE, SUITES
Supported Families
Arria GX, Cyclone II, HardCopy II, Stratix II
Features
Common Avalon Streaming (Avalon-St) Interface And Avalon-St Video Protocol
Core Architecture
FPGA
Core Sub-architecture
Arria, Cyclone, Stratix
Rohs Compliant
NA
Lead Free Status / RoHS Status
na
- Current page: 40 of 202
- Download datasheet (6Mb)
3–4
Alpha Blending Mixer
Table 3–4. Alpha Blending Mixer Parameter Settings
Chroma Resampler
Table 3–5. Chroma Resampler Parameter Settings (Part 1 of 2)
Video and Image Processing Suite User Guide
Maximum layer
width
Maximum layer
height
Bits per pixel per
color plane
Number of color
planes in sequence
Number of color
planes in parallel
Number of layers
being mixed
Alpha blending
Alpha bits per pixel 2, 4, 8
Maximum width
Maximum height
Bits per pixel per
color plane
Color plane
configuration
Input Format
Output Format
Horizontal Filtering
Algorithm
Parameter
Parameter
(1)
(1)
32–2600, Default = 1,024
32–2600, Default = 768
4–20, Default = 8
1–3
1–3
2–12
On or Off
32–2600, Default = 256
32–2600, Default = 256
4–20, Default = 8
Sequence, Parallel
4:4:4, 4:2:2, 4:2:0
4:4:4, 4:2:2, 4:2:0
Filtered,
Nearest Neighbor
Table 3–4
Table 3–5
Value
Value
shows the Alpha Blending Mixer MegaCore function parameters.
shows the Chroma Resampler MegaCore function parameters.
Choose the maximum image width in pixels.
Choose the maximum image height in pixels.
Choose the number of bits per pixel (per color plane).
There must always be three color planes for this function but you can
choose whether the three color planes are transmitted in sequence or in
parallel.
Choose the format/sampling rate format for the input frames. Note that the
input and output formats must be different.
Choose the format/sampling rate format for the output frames. Note that
the input and output formats must be different.
Choose the algorithm to use in the horizontal direction when re-sampling
data to or from 4:4:4.
Choose the maximum image width for the layer background in pixels. No
layer width can be greater than the background layer width. The
maximum image width is the default width for all layers at start-up.
Choose the maximum image height for the layer background in pixels. No
layer height can be greater than the background layer height. The
maximum image height is the default height for all layers at start-up.
Choose the number of bits per pixel (per color plane).
Choose the number of color planes that are sent in sequence over one
data connection. For example, a value of 3 for R'G'B' R'G'B' R'G'B'.
Choose the number of color planes in parallel.
Choose the number of image layers to overlay. Higher number layers are
mixed on top of lower layer numbers. The background layer is always
layer 0.
When on, alpha data sink ports are generated for each layer (including an
unused port alpha_in_0 for the background layer). This requires a
stream of alpha values; one value for each pixel. When off, no alpha data
sink ports are generated, and the image layers are fully opaque.
Choose the number of bits used to represent the alpha coefficient.
Description
Description
January 2011 Altera Corporation
Chapter 3: Parameter Settings
Alpha Blending Mixer
Related parts for IPSR-VIDEO
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
CYCLONE II STARTER KIT EP2C20N
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 35 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 15 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 30 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 7ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Classic EPLD
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet: