IPSR-VIDEO Altera, IPSR-VIDEO Datasheet - Page 172

• Manufacturer Part Number: IPSR-VIDEO
• Description: RENEWAL Of IPS-VIDEO
• Manufacturer: Altera
• Series: IP Suitesr

Specifications of IPSR-VIDEO

• Software Application: IP CORE, SUITES
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Features: Common Avalon Streaming (Avalon-St) Interface And Avalon-St Video Protocol
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

6–16
Table 6–12. Frame Buffer Signals (Part 3 of 3)
Frame Reader
Table 6–13. Frame Reader Signals (Part 1 of 2)
Video and Image Processing Suite User Guide
writer_control_av_chipselect
writer_control_av_readdata
writer_control_av_write
writer_control_av_writedata
Notes to
(1) Additional clock and reset signals are available when Use separate clocks for the Avalon-MM master interfaces is on in the parameter editor.
(2) These ports are present only if the control interface for the reader component has been enabled.
(3) These ports are present only if the control interface for the writer component has been enabled
clock
reset
dout_data
dout_endofpacket
dout_ready
dout_startofpacket
dout_valid
slave_av_address
slave_av_read
slave_av_readdata
slave_av_write
Table
6–12:
Signal
Signal
Table 6–13
function.
shows the input and output signals for the Frame Reader MegaCore
Direction
In
Out
In
In
Direction
In
In
Out
Out
In
Out
Out
In
In
Out
In
writer_control slave port Avalon-MM chipselect signal. The
writer_control port ignores all other signals unless this signal
is asserted.
writer_control slave port Avalon-MM readdata bus. These
output lines are used for read transfers.
writer_control slave port Avalon-MM write signal. When this
signal is asserted, the writer_control port accepts new data
from the writedata bus.
writer_control slave port Avalon-MM writedata bus. These
input lines are used for write transfers.
The main system clock. The MegaCore function operates on the
rising edge of the clock signal.
The MegaCore function is asynchronously reset when reset is
asserted high. The reset must be de-asserted synchronously with
respect to the rising edge of the clock signal.
dout port Avalon-ST data bus. Pixel data is
transferred out of the MegaCore function over this bus.
dout port Avalon-ST endofpacket signal. This signal
marks the end of an Avalon-ST packet.
dout port Avalon-ST ready signal. This signal is
asserted by the downstream device when it is able to receive data.
dout port Avalon-ST startofpacket signal. This
signal marks the start of an Avalon-ST packet.
dout port Avalon-ST valid signal. This signal is
asserted when the MegaCore function outputs data.
slave port Avalon-MM address. Specifies a word offset
into the slave address space.
slave port Avalon-MM read signal. When this signal is
asserted, the slave port drives new data onto the read data bus.
slave port Avalon-MM readdata bus. These output
lines are used for read transfers.
slave port Avalon-MM write signal. When this signal is
asserted, the gamma_lut port accepts new data from the
writedata bus.
(3)
Description
(3)
Description
January 2011 Altera Corporation
(3)
(3)
Chapter 6: Signals
Frame Reader