IPSR-VIDEO Altera, IPSR-VIDEO Datasheet - Page 35

• Manufacturer Part Number: IPSR-VIDEO
• Description: RENEWAL Of IPS-VIDEO
• Manufacturer: Altera
• Series: IP Suitesr

Specifications of IPSR-VIDEO

• Software Application: IP CORE, SUITES
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Features: Common Avalon Streaming (Avalon-St) Interface And Avalon-St Video Protocol
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 2: Getting Started with Altera IP Cores
Generated Files
Generated Files
Table 2–1. Generated Files
January 2011 Altera Corporation
<variation name>.bsf
<variation name>.cmp
Simulate the System
File Name
f
f
f
1
6. Click Generate to generate the system. Qsys generates the system and produces
7. In the Quartus II software, click Add/Remove Files in Project and add the .qip file
8. Compile your project in the Quartus II software.
During system generation, Qsys generates a functional simulation model—or
example design that includes a testbench—which you can use to simulate your
system in any Altera-supported simulation tool.
For information about the latest Altera-supported simulation tools, refer to the
Quartus II Software Release
For general information about simulating Altera IP cores, refer to
Designs
For information about simulating Qsys systems, refer to the
section in volume 1 of the Quartus II Handbook.
Table 2–1
directory.
The names and types of files vary depending on the variation name and HDL type
you specify during parameterization For example, a different set of files are created
based on whether you create your design in Verilog HDL or VHDL.
For a description of the signals that the MegaCore function variation supports, refer to
Chapter 6,
the <system name>.qip file that contains the assignments and information required
to process the IP core or system in the Quartus II Compiler.
to the project.
(Note 1)
Quartus II block symbol file for the MegaCore function variation. You can use this file in the
Quartus II block diagram editor.
A VHDL component declaration file for the MegaCore function variation. Add the contents
of this file to any VHDL architecture that instantiates the MegaCore function.
in volume 3 of the Quartus II Handbook.
describes the generated files and other files that may be in your project
Signals.
(Part 1 of 2)
Notes.
Description
Video and Image Processing Suite User Guide
System Design with Qsys
Simulating Altera
2–9