IPSR-VIDEO Altera, IPSR-VIDEO Datasheet - Page 170

• Manufacturer Part Number: IPSR-VIDEO
• Description: RENEWAL Of IPS-VIDEO
• Manufacturer: Altera
• Series: IP Suitesr

Specifications of IPSR-VIDEO

• Software Application: IP CORE, SUITES
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Features: Common Avalon Streaming (Avalon-St) Interface And Avalon-St Video Protocol
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

6–14
Table 6–11. Deinterlacer Signals (Part 4 of 4)
Frame Buffer
Table 6–12. Frame Buffer Signals (Part 1 of 3)
Video and Image Processing Suite User Guide
write_master_av_writedata
Note to
(1) The signals associated with the write_master and read_master ports are present only when buffering is used.
(2) When the motion-adaptive algorithm is selected, two read master interfaces are used.
(3) When the motion-adaptive algorithm is selected and motion bleed is turned on, one additional read master (motion_read_master) and one
(4) Additional clock and reset signals are available when Use separate clocks for the Avalon-MM master interfaces is on in the parameter editor.
(5) The signals associated with the ma_control port are not present unless run-time control of the motion adaptive blending is enabled.
(6) The signals associated with the ker_writer_control port are not present unless run-time control for locked frame rate conversion is enabled.
clock
reset
din_data
din_endofpacket
din_ready
din_startofpacket
din_valid
dout_data
dout_endofpacket
dout_ready
dout_startofpacket
dout_valid
read_master_av_address
additional write master (motion_write_master) port are used to read and update motion values.
Table
6–11:
Signal
Signal
Table 6–12
function.
shows the input and output signals for the Frame Buffer MegaCore
Direction
In
In
In
In
Out
In
In
Out
Out
In
Out
Out
Out
Direction
Out
The main system clock. The MegaCore function operates on the
rising edge of the clock signal.
The MegaCore function is asynchronously reset when reset is
asserted high. The reset must be de-asserted synchronously with
respect to the rising edge of the clock signal.
din port Avalon-ST data bus. Pixel data is transferred into the
MegaCore function over this bus.
din port Avalon-ST endofpacket signal. This signal marks the
end of an Avalon-ST packet.
din port Avalon-ST ready signal. This signal indicates when the
MegaCore function is ready to receive data.
din port Avalon-ST startofpacket signal. This signal marks the
start of an Avalon-ST packet.
din port Avalon-ST valid signal. This signal identifies the cycles
when the port should input data.
dout port Avalon-ST data bus. Pixel data is transferred out of the
MegaCore function over this bus.
dout port Avalon-ST endofpacket signal. This signal marks the
end of an Avalon-ST packet.
dout port Avalon-ST ready signal. This signal is asserted by the
downstream device when it is able to receive data.
dout port Avalon-ST startofpacket signal. This signal marks
the start of an Avalon-ST packet.
dout port Avalon-ST valid signal. This signal is asserted when
the MegaCore function is outputs data.
read_master port Avalon-MM address bus. Specifies a byte
address in the Avalon-MM address space.
write_master port Avalon-MM writedata bus. These
output lines carry data for write transfers. (1),
Description
Description
January 2011 Altera Corporation
Chapter 6: Signals
(3)
Frame Buffer