IPSR-VIDEO Altera, IPSR-VIDEO Datasheet - Page 177

• Manufacturer Part Number: IPSR-VIDEO
• Description: RENEWAL Of IPS-VIDEO
• Manufacturer: Altera
• Series: IP Suitesr

Specifications of IPSR-VIDEO

• Software Application: IP CORE, SUITES
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Features: Common Avalon Streaming (Avalon-St) Interface And Avalon-St Video Protocol
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 6: Signals
Switch
Table 6–17. Scaler II Signals (Part 2 of 2)
Switch
Table 6–18. Switch Signals (Part 1 of 2)
January 2011 Altera Corporation
control_read
control_readdata
control_waitrequest
control_write
control_writedata
din_data
din_endofpacket
din_ready
din_startofpacket
din_valid
dout_data
dout_endofpacket
dout_ready
dout_startofpacket
dout_valid
Note to
(1) These ports are not present if you turn off Enable runtime control of input/output frame size and select Bilinear for Scaling algorithm in the
clock
reset
parameter editor.
Table 6–17
Signal
Signal
Table 6–18
Direction
In
Out
Out
In
In
In
In
Out
In
In
Out
Out
In
Out
Out
shows the input and output signals for the Switch MegaCore function.
Direction
In
In
control slave port Avalon-MM read signal. When you assert this signal,
the control port outputs new data at readdata.
control slave port Avalon-MM readdata bus. Output lines for read
transfers.
control slave port Avalon-MM waitrequest signal.
control slave port Avalon-MM write signal. When you assert this signal,
the control port accepts new data from the writedata bus.
control slave port Avalon-MM writedata bus. Input lines for write
transfers.
din port Avalon-ST data bus. Transfers pixel data into the MegaCore
function.
din port Avalon-ST endofpacket signal. This signal marks the end of an
Avalon-ST packet.
din port Avalon-ST ready signal. This signal indicates when the MegaCore
function is ready to receive data.
din port Avalon-ST startofpacket signal. This signal marks the start of
an Avalon-ST packet.
din port Avalon-ST valid signal. This signal identifies the cycles when the
port should input data.
dout port Avalon-ST data bus. Pixel data is transferred out of the
MegaCore function over this bus.
dout port Avalon-ST endofpacket signal. This signal marks the end of an
Avalon-ST packet.
dout port Avalon-ST ready signal. This signal is asserted by the
downstream device when it is able to receive data.
dout port Avalon-ST startofpacket signal. This signal marks the start of
an Avalon-ST packet.
dout port Avalon-ST valid signal. This signal is asserted when the
MegaCore function outputs data.
The main system clock. The MegaCore function operates on the rising
edge of the clock signal.
The MegaCore function is asynchronously reset when reset is
asserted high. The reset must be de-asserted synchronously with
respect to the rising edge of the clock signal.
(1)
(1)
Description
Description
Video and Image Processing Suite User Guide
(1)
(1)
(1)
6–21